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  1. 26 Jan, 2000 4 commits
  2. 25 Jan, 2000 26 commits
  3. 24 Jan, 2000 10 commits
    • sewardj's avatar
      [project @ 2000-01-24 18:33:34 by sewardj] · 3ba6150e
      sewardj authored
      Start a NOTES file, recording known but un-fixed nativeGen bugs.
    • sewardj's avatar
      [project @ 2000-01-24 18:28:53 by sewardj] · 243924b8
      sewardj authored
      Fix syntax errors in #ifdef'd Alpha/Sparc bits.
    • sewardj's avatar
      [project @ 2000-01-24 18:25:17 by sewardj] · 8f43a965
      sewardj authored
      Insert large commit message re x86 FP rehash as a comment.
    • sewardj's avatar
      [project @ 2000-01-24 18:22:07 by sewardj] · 9ac31f7c
      sewardj authored
      ARR_HDR_SIZE --> ARR_WORDS_HDR_SIZE, and derived quantities in
      Constants.h, Constants.lhs et al are similarly renamed.
      new constant ARR_PTRS_HDR_SIZE, with corresponding derivatives.
    • rrt's avatar
      [project @ 2000-01-24 17:44:52 by rrt] · c81c46d2
      rrt authored
      Changed default paper size for SGML output to A4 (%paper-type%).
    • sewardj's avatar
      [project @ 2000-01-24 17:24:23 by sewardj] · e2a7f079
      sewardj authored
      Major reworking of the x86 floating point code generation.
      Intel, in their infinite wisdom, selected a stack model for floating
      point registers on x86.  That might have made sense back in 1979 --
      nowadays we can see it for the nonsense it really is.  A stack model
      fits poorly with the existing nativeGen infrastructure, which assumes
      flat integer and FP register sets.  Prior to this commit, nativeGen
      could not generate correct x86 FP code -- to do so would have meant
      somehow working the register-stack paradigm into the register
      allocator and spiller, which sounds very difficult.
      We have decided to cheat, and go for a simple fix which requires no
      infrastructure modifications, at the expense of generating ropey but
      correct FP code.  All notions of the x86 FP stack and its insns have
      been removed.  Instead, we pretend (to the instruction selector and
      register allocator) that x86 has six floating point registers, %fake0
      .. %fake5, which can be used in the usual flat manner.  We further
      claim that x86 has floating point instructions very similar to SPARC
      and Alpha, that is, a simple 3-operand register-register arrangement.
      Code generation and register allocation proceed on this basis.
      When we come to print out the final assembly, our convenient fiction
      is converted to dismal reality.  Each fake instruction is
      independently converted to a series of real x86 instructions.
      %fake0 .. %fake5 are mapped to %st(0) .. %st(5).  To do reg-reg
      arithmetic operations, the two operands are pushed onto the top of the
      FP stack, the operation done, and the result copied back into the
      relevant register.  There are only six %fake registers because 2 are
      needed for the translation, and x86 has 8 in total.
      The translation is inefficient but is simple and it works.  A cleverer
      translation would handle a sequence of insns, simulating the FP stack
      contents, would not impose a fixed mapping from %fake to %st regs, and
      hopefully could avoid most of the redundant reg-reg moves of the
      current translation.
    • rrt's avatar
      [project @ 2000-01-24 17:09:40 by rrt] · 55400852
      rrt authored
      Added table example.
    • panne's avatar
      [project @ 2000-01-24 16:55:45 by panne] · f5b98196
      panne authored
      Added autoconf magic for size/alignment of some more C types
    • rrt's avatar
      [project @ 2000-01-24 16:47:24 by rrt] · 7db602a0
      rrt authored
      Changed double quotes to “ and ”. Improvements to Windows
      installation instructions.
    • simonmar's avatar
      [project @ 2000-01-24 15:40:57 by simonmar] · 17a29073
      simonmar authored
      Update the Hall of Fame.