1. 01 Jul, 2019 1 commit
  2. 28 Jun, 2019 4 commits
    • Ben Gamari's avatar
      rts: Assert that LDV profiling isn't used with parallel GC · bd660ede
      Ben Gamari authored
      I'm not entirely sure we are careful about ensuring this; this is a
      last-ditch check.
      bd660ede
    • Travis Whitaker's avatar
      Correct closure observation, construction, and mutation on weak memory machines. · 11bac115
      Travis Whitaker authored
      Here the following changes are introduced:
          - A read barrier machine op is added to Cmm.
          - The order in which a closure's fields are read and written is changed.
          - Memory barriers are added to RTS code to ensure correctness on
            out-or-order machines with weak memory ordering.
      
      Cmm has a new CallishMachOp called MO_ReadBarrier. On weak memory machines, this
      is lowered to an instruction that ensures memory reads that occur after said
      instruction in program order are not performed before reads coming before said
      instruction in program order. On machines with strong memory ordering properties
      (e.g. X86, SPARC in TSO mode) no such instruction is necessary, so
      MO_ReadBarrier is simply erased. However, such an instruction is necessary on
      weakly ordered machines, e.g. ARM and PowerPC.
      
      Weam memory ordering has consequences for how closures are observed and mutated.
      For example, consider a closure that needs to be upda...
      11bac115
    • Artem Pelenitsyn's avatar
      typo in the docs for DynFlags.hs · ef6d9a50
      Artem Pelenitsyn authored
      ef6d9a50
    • Sylvain Henry's avatar
      4ec233ec
  3. 27 Jun, 2019 9 commits
  4. 26 Jun, 2019 16 commits
  5. 25 Jun, 2019 9 commits
  6. 24 Jun, 2019 1 commit