diff --git a/ghc/compiler/coreSyn/CoreSyn.hi-boot b/ghc/compiler/coreSyn/CoreSyn.hi-boot
index 3ea40f47d992d517a3045b8a3575383078aff93a..c2fb8bf8b88977fa7680c76a2dba5b6b64c371b6 100644
--- a/ghc/compiler/coreSyn/CoreSyn.hi-boot
+++ b/ghc/compiler/coreSyn/CoreSyn.hi-boot
@@ -8,7 +8,7 @@ _declarations_
 1 data Expr b ;
 
 1 data CoreRule ;
-1 type CoreRules = [CoreRule] ;
+1 data CoreRules = Rules [CoreRule] VarSet.IdOrTyVarSet ;;
 1 emptyCoreRules _:_ CoreRules ;;
 1 seqRules _:_ CoreRules -> PrelBase.() ;;
 1 isEmptyCoreRules _:_ CoreRules -> PrelBase.Bool ;;
diff --git a/ghc/compiler/coreSyn/CoreSyn.hi-boot-5 b/ghc/compiler/coreSyn/CoreSyn.hi-boot-5
index d8ad7ffe698030d95aed4a7203597f3f9630055c..2ddc75bb324c897efe8773400ab4b582c14cb996 100644
--- a/ghc/compiler/coreSyn/CoreSyn.hi-boot-5
+++ b/ghc/compiler/coreSyn/CoreSyn.hi-boot-5
@@ -6,7 +6,7 @@ __export CoreSyn CoreExpr CoreRules CoreRule emptyCoreRules isEmptyCoreRules seq
 1 data Expr b ;
 
 1 data CoreRule ;
-1 type CoreRules = [CoreRule] ;
+1 data CoreRules = Rules [CoreRule] VarSet.IdOrTyVarSet ;
 1 emptyCoreRules :: CoreRules ;
 1 seqRules :: CoreRules -> PrelBase.Z0T ;
 1 isEmptyCoreRules :: CoreRules -> PrelBase.Bool ;