add support for ARM hard-float ABI (fixes #5914)

This patch enhances Platform's ArchARM to include ARM ABI value. It also
tweaks configure machinery to detect hard-float ABI and to set it wherever
needed. Finally when hard-float ABI is in use, pass appropriate compiler
option to the LLVM's llc. Fixes #5914.

aclocal.m4

@@ -171,7 +171,7 @@ AC_DEFUN([FPTOOLS_SET_HASKELL_PLATFORM_VARS],
             ;;
         arm)
             GET_ARM_ISA()
-            test -z "[$]2" || eval "[$]2=\"ArchARM {armISA = \$ARM_ISA, armISAExt = \$ARM_ISA_EXT}\""
+            test -z "[$]2" || eval "[$]2=\"ArchARM {armISA = \$ARM_ISA, armISAExt = \$ARM_ISA_EXT, armABI = \$ARM_ABI}\""
             ;;
         alpha|mips|mipseb|mipsel|hppa|hppa1_1|ia64|m68k|rs6000|s390|s390x|sparc64|vax)
             test -z "[$]2" || eval "[$]2=ArchUnknown"

compiler/main/DriverPipeline.hs

@@ -1372,7 +1372,8 @@ runPhase LlvmLlc input_fn dflags
                     SysTools.Option "-o", SysTools.FileOption "" output_fn]
                 ++ map SysTools.Option lc_opts
                 ++ [SysTools.Option tbaa]
-                ++ map SysTools.Option fpOpts)
+                ++ map SysTools.Option fpOpts
+                ++ map SysTools.Option abiOpts)
 
     return (next_phase, output_fn)
   where
@@ -1384,12 +1385,19 @@ runPhase LlvmLlc input_fn dflags
         -- while compiling GHC source code. It's probably due to fact that it
         -- does not enable VFP by default. Let's do this manually here
         fpOpts = case platformArch (targetPlatform dflags) of 
-                   ArchARM ARMv7 ext -> if (elem VFPv3 ext)
+                   ArchARM ARMv7 ext _ -> if (elem VFPv3 ext)
                                       then ["-mattr=+v7,+vfp3"]
                                       else if (elem VFPv3D16 ext)
                                            then ["-mattr=+v7,+vfp3,+d16"]
                                            else []
                    _                 -> []
+        -- On Ubuntu/Debian with ARM hard float ABI, LLVM's llc still
+        -- compiles into soft-float ABI. We need to explicitly set abi
+        -- to hard
+        abiOpts = case platformArch (targetPlatform dflags) of
+                    ArchARM ARMv7 _ HARD -> ["-float-abi=hard"]
+                    ArchARM ARMv7 _ _    -> []
+                    _                    -> []
 
 -----------------------------------------------------------------------------
 -- LlvmMangle phase
@@ -1538,8 +1546,8 @@ mkNoteObjsToLinkIntoBinary dflags dep_packages = do
 
             elfSectionNote :: String
             elfSectionNote = case platformArch (targetPlatform dflags) of
-                               ArchARM _ _ -> "%note"
-                               _           -> "@note"
+                               ArchARM _ _ _ -> "%note"
+                               _             -> "@note"
 
 -- The "link info" is a string representing the parameters of the
 -- link.  We save this information in the binary, and the next time we

compiler/nativeGen/AsmCodeGen.lhs

@@ -200,7 +200,7 @@ nativeCodeGen dflags h us cmms
                          ,ncgExpandTop              = map SPARC.CodeGen.Expand.expandTop
                          ,ncgMakeFarBranches        = id
                      }
-                 ArchARM _ _ ->
+                 ArchARM _ _ _ ->
                      panic "nativeCodeGen: No NCG for ARM"
                  ArchPPC_64 ->
                      panic "nativeCodeGen: No NCG for PPC 64"

compiler/nativeGen/RegAlloc/Graph/TrivColorable.hs

@@ -107,13 +107,13 @@ trivColorable
 trivColorable platform virtualRegSqueeze realRegSqueeze RcInteger conflicts exclusions
         | let !cALLOCATABLE_REGS_INTEGER
                   = iUnbox (case platformArch platform of
-                            ArchX86     -> 3
-                            ArchX86_64  -> 5
-                            ArchPPC     -> 16
-                            ArchSPARC   -> 14
-                            ArchPPC_64  -> panic "trivColorable ArchPPC_64"
-                            ArchARM _ _ -> panic "trivColorable ArchARM"
-                            ArchUnknown -> panic "trivColorable ArchUnknown")
+                            ArchX86       -> 3
+                            ArchX86_64    -> 5
+                            ArchPPC       -> 16
+                            ArchSPARC     -> 14
+                            ArchPPC_64    -> panic "trivColorable ArchPPC_64"
+                            ArchARM _ _ _ -> panic "trivColorable ArchARM"
+                            ArchUnknown   -> panic "trivColorable ArchUnknown")
         , count2        <- accSqueeze (_ILIT(0)) cALLOCATABLE_REGS_INTEGER
                                 (virtualRegSqueeze RcInteger)
                                 conflicts
@@ -127,13 +127,13 @@ trivColorable platform virtualRegSqueeze realRegSqueeze RcInteger conflicts excl
 trivColorable platform virtualRegSqueeze realRegSqueeze RcFloat conflicts exclusions
         | let !cALLOCATABLE_REGS_FLOAT
                   = iUnbox (case platformArch platform of
-                            ArchX86     -> 0
-                            ArchX86_64  -> 0
-                            ArchPPC     -> 0
-                            ArchSPARC   -> 22
-                            ArchPPC_64  -> panic "trivColorable ArchPPC_64"
-                            ArchARM _ _ -> panic "trivColorable ArchARM"
-                            ArchUnknown -> panic "trivColorable ArchUnknown")
+                            ArchX86       -> 0
+                            ArchX86_64    -> 0
+                            ArchPPC       -> 0
+                            ArchSPARC     -> 22
+                            ArchPPC_64    -> panic "trivColorable ArchPPC_64"
+                            ArchARM _ _ _ -> panic "trivColorable ArchARM"
+                            ArchUnknown   -> panic "trivColorable ArchUnknown")
         , count2        <- accSqueeze (_ILIT(0)) cALLOCATABLE_REGS_FLOAT
                                 (virtualRegSqueeze RcFloat)
                                 conflicts
@@ -147,13 +147,13 @@ trivColorable platform virtualRegSqueeze realRegSqueeze RcFloat conflicts exclus
 trivColorable platform virtualRegSqueeze realRegSqueeze RcDouble conflicts exclusions
         | let !cALLOCATABLE_REGS_DOUBLE
                   = iUnbox (case platformArch platform of
-                            ArchX86     -> 6
-                            ArchX86_64  -> 0
-                            ArchPPC     -> 26
-                            ArchSPARC   -> 11
-                            ArchPPC_64  -> panic "trivColorable ArchPPC_64"
-                            ArchARM _ _ -> panic "trivColorable ArchARM"
-                            ArchUnknown -> panic "trivColorable ArchUnknown")
+                            ArchX86       -> 6
+                            ArchX86_64    -> 0
+                            ArchPPC       -> 26
+                            ArchSPARC     -> 11
+                            ArchPPC_64    -> panic "trivColorable ArchPPC_64"
+                            ArchARM _ _ _ -> panic "trivColorable ArchARM"
+                            ArchUnknown   -> panic "trivColorable ArchUnknown")
         , count2        <- accSqueeze (_ILIT(0)) cALLOCATABLE_REGS_DOUBLE
                                 (virtualRegSqueeze RcDouble)
                                 conflicts
@@ -167,13 +167,13 @@ trivColorable platform virtualRegSqueeze realRegSqueeze RcDouble conflicts exclu
 trivColorable platform virtualRegSqueeze realRegSqueeze RcDoubleSSE conflicts exclusions
         | let !cALLOCATABLE_REGS_SSE
                   = iUnbox (case platformArch platform of
-                            ArchX86     -> 8
-                            ArchX86_64  -> 10
-                            ArchPPC     -> 0
-                            ArchSPARC   -> 0
-                            ArchPPC_64  -> panic "trivColorable ArchPPC_64"
-                            ArchARM _ _ -> panic "trivColorable ArchARM"
-                            ArchUnknown -> panic "trivColorable ArchUnknown")
+                            ArchX86       -> 8
+                            ArchX86_64    -> 10
+                            ArchPPC       -> 0
+                            ArchSPARC     -> 0
+                            ArchPPC_64    -> panic "trivColorable ArchPPC_64"
+                            ArchARM _ _ _ -> panic "trivColorable ArchARM"
+                            ArchUnknown   -> panic "trivColorable ArchUnknown")
         , count2        <- accSqueeze (_ILIT(0)) cALLOCATABLE_REGS_SSE
                                 (virtualRegSqueeze RcDoubleSSE)
                                 conflicts

compiler/nativeGen/RegAlloc/Linear/FreeRegs.hs

@@ -68,11 +68,11 @@ instance FR SPARC.FreeRegs where
 maxSpillSlots :: Platform -> Int
 maxSpillSlots platform
               = case platformArch platform of
-                ArchX86     -> X86.Instr.maxSpillSlots True  -- 32bit
-                ArchX86_64  -> X86.Instr.maxSpillSlots False -- not 32bit
-                ArchPPC     -> PPC.Instr.maxSpillSlots
-                ArchSPARC   -> SPARC.Instr.maxSpillSlots
-                ArchARM _ _ -> panic "maxSpillSlots ArchARM"
-                ArchPPC_64  -> panic "maxSpillSlots ArchPPC_64"
-                ArchUnknown -> panic "maxSpillSlots ArchUnknown"
+                ArchX86       -> X86.Instr.maxSpillSlots True  -- 32bit
+                ArchX86_64    -> X86.Instr.maxSpillSlots False -- not 32bit
+                ArchPPC       -> PPC.Instr.maxSpillSlots
+                ArchSPARC     -> SPARC.Instr.maxSpillSlots
+                ArchARM _ _ _ -> panic "maxSpillSlots ArchARM"
+                ArchPPC_64    -> panic "maxSpillSlots ArchPPC_64"
+                ArchUnknown   -> panic "maxSpillSlots ArchUnknown"
 

compiler/nativeGen/RegAlloc/Linear/Main.hs

@@ -180,13 +180,13 @@ linearRegAlloc
 linearRegAlloc dflags first_id block_live sccs
  = let platform = targetPlatform dflags
    in case platformArch platform of
-      ArchX86     -> linearRegAlloc' platform (frInitFreeRegs :: X86.FreeRegs)   first_id block_live sccs
-      ArchX86_64  -> linearRegAlloc' platform (frInitFreeRegs :: X86.FreeRegs)   first_id block_live sccs
-      ArchSPARC   -> linearRegAlloc' platform (frInitFreeRegs :: SPARC.FreeRegs) first_id block_live sccs
-      ArchPPC     -> linearRegAlloc' platform (frInitFreeRegs :: PPC.FreeRegs)   first_id block_live sccs
-      ArchARM _ _ -> panic "linearRegAlloc ArchARM"
-      ArchPPC_64  -> panic "linearRegAlloc ArchPPC_64"
-      ArchUnknown -> panic "linearRegAlloc ArchUnknown"
+      ArchX86       -> linearRegAlloc' platform (frInitFreeRegs :: X86.FreeRegs)   first_id block_live sccs
+      ArchX86_64    -> linearRegAlloc' platform (frInitFreeRegs :: X86.FreeRegs)   first_id block_live sccs
+      ArchSPARC     -> linearRegAlloc' platform (frInitFreeRegs :: SPARC.FreeRegs) first_id block_live sccs
+      ArchPPC       -> linearRegAlloc' platform (frInitFreeRegs :: PPC.FreeRegs)   first_id block_live sccs
+      ArchARM _ _ _ -> panic "linearRegAlloc ArchARM"
+      ArchPPC_64    -> panic "linearRegAlloc ArchPPC_64"
+      ArchUnknown   -> panic "linearRegAlloc ArchUnknown"
 
 linearRegAlloc'
         :: (FR freeRegs, PlatformOutputable instr, Instruction instr)

compiler/nativeGen/TargetReg.hs

@@ -50,35 +50,35 @@ import qualified SPARC.Regs     as SPARC
 targetVirtualRegSqueeze :: Platform -> RegClass -> VirtualReg -> FastInt
 targetVirtualRegSqueeze platform
     = case platformArch platform of
-      ArchX86     -> X86.virtualRegSqueeze
-      ArchX86_64  -> X86.virtualRegSqueeze
-      ArchPPC     -> PPC.virtualRegSqueeze
-      ArchSPARC   -> SPARC.virtualRegSqueeze
-      ArchPPC_64  -> panic "targetVirtualRegSqueeze ArchPPC_64"
-      ArchARM _ _ -> panic "targetVirtualRegSqueeze ArchARM"
-      ArchUnknown -> panic "targetVirtualRegSqueeze ArchUnknown"
+      ArchX86       -> X86.virtualRegSqueeze
+      ArchX86_64    -> X86.virtualRegSqueeze
+      ArchPPC       -> PPC.virtualRegSqueeze
+      ArchSPARC     -> SPARC.virtualRegSqueeze
+      ArchPPC_64    -> panic "targetVirtualRegSqueeze ArchPPC_64"
+      ArchARM _ _ _ -> panic "targetVirtualRegSqueeze ArchARM"
+      ArchUnknown   -> panic "targetVirtualRegSqueeze ArchUnknown"
 
 targetRealRegSqueeze :: Platform -> RegClass -> RealReg -> FastInt
 targetRealRegSqueeze platform
     = case platformArch platform of
-      ArchX86     -> X86.realRegSqueeze
-      ArchX86_64  -> X86.realRegSqueeze
-      ArchPPC     -> PPC.realRegSqueeze
-      ArchSPARC   -> SPARC.realRegSqueeze
-      ArchPPC_64  -> panic "targetRealRegSqueeze ArchPPC_64"
-      ArchARM _ _ -> panic "targetRealRegSqueeze ArchARM"
-      ArchUnknown -> panic "targetRealRegSqueeze ArchUnknown"
+      ArchX86       -> X86.realRegSqueeze
+      ArchX86_64    -> X86.realRegSqueeze
+      ArchPPC       -> PPC.realRegSqueeze
+      ArchSPARC     -> SPARC.realRegSqueeze
+      ArchPPC_64    -> panic "targetRealRegSqueeze ArchPPC_64"
+      ArchARM _ _ _ -> panic "targetRealRegSqueeze ArchARM"
+      ArchUnknown   -> panic "targetRealRegSqueeze ArchUnknown"
 
 targetClassOfRealReg :: Platform -> RealReg -> RegClass
 targetClassOfRealReg platform
     = case platformArch platform of
-      ArchX86     -> X86.classOfRealReg
-      ArchX86_64  -> X86.classOfRealReg
-      ArchPPC     -> PPC.classOfRealReg
-      ArchSPARC   -> SPARC.classOfRealReg
-      ArchPPC_64  -> panic "targetClassOfRealReg ArchPPC_64"
-      ArchARM _ _ -> panic "targetClassOfRealReg ArchARM"
-      ArchUnknown -> panic "targetClassOfRealReg ArchUnknown"
+      ArchX86       -> X86.classOfRealReg
+      ArchX86_64    -> X86.classOfRealReg
+      ArchPPC       -> PPC.classOfRealReg
+      ArchSPARC     -> SPARC.classOfRealReg
+      ArchPPC_64    -> panic "targetClassOfRealReg ArchPPC_64"
+      ArchARM _ _ _ -> panic "targetClassOfRealReg ArchARM"
+      ArchUnknown   -> panic "targetClassOfRealReg ArchUnknown"
 
 -- TODO: This should look at targetPlatform too
 targetWordSize :: Size
@@ -87,24 +87,24 @@ targetWordSize = intSize wordWidth
 targetMkVirtualReg :: Platform -> Unique -> Size -> VirtualReg
 targetMkVirtualReg platform
     = case platformArch platform of
-      ArchX86     -> X86.mkVirtualReg
-      ArchX86_64  -> X86.mkVirtualReg
-      ArchPPC     -> PPC.mkVirtualReg
-      ArchSPARC   -> SPARC.mkVirtualReg
-      ArchPPC_64  -> panic "targetMkVirtualReg ArchPPC_64"
-      ArchARM _ _ -> panic "targetMkVirtualReg ArchARM"
-      ArchUnknown -> panic "targetMkVirtualReg ArchUnknown"
+      ArchX86       -> X86.mkVirtualReg
+      ArchX86_64    -> X86.mkVirtualReg
+      ArchPPC       -> PPC.mkVirtualReg
+      ArchSPARC     -> SPARC.mkVirtualReg
+      ArchPPC_64    -> panic "targetMkVirtualReg ArchPPC_64"
+      ArchARM _ _ _ -> panic "targetMkVirtualReg ArchARM"
+      ArchUnknown   -> panic "targetMkVirtualReg ArchUnknown"
 
 targetRegDotColor :: Platform -> RealReg -> SDoc
 targetRegDotColor platform
     = case platformArch platform of
-      ArchX86     -> X86.regDotColor platform
-      ArchX86_64  -> X86.regDotColor platform
-      ArchPPC     -> PPC.regDotColor
-      ArchSPARC   -> SPARC.regDotColor
-      ArchPPC_64  -> panic "targetRegDotColor ArchPPC_64"
-      ArchARM _ _ -> panic "targetRegDotColor ArchARM"
-      ArchUnknown -> panic "targetRegDotColor ArchUnknown"
+      ArchX86       -> X86.regDotColor platform
+      ArchX86_64    -> X86.regDotColor platform
+      ArchPPC       -> PPC.regDotColor
+      ArchSPARC     -> SPARC.regDotColor
+      ArchPPC_64    -> panic "targetRegDotColor ArchPPC_64"
+      ArchARM _ _ _ -> panic "targetRegDotColor ArchARM"
+      ArchUnknown   -> panic "targetRegDotColor ArchUnknown"
 
 
 targetClassOfReg :: Platform -> Reg -> RegClass

compiler/utils/Platform.hs

@@ -7,6 +7,7 @@ module Platform (
         OS(..),
         ArmISA(..),
         ArmISAExt(..),
+        ArmABI(..),
 
         target32Bit,
         osElfTarget
@@ -41,7 +42,9 @@ data Arch
         | ArchSPARC
         | ArchARM
           { armISA    :: ArmISA
-          , armISAExt :: [ArmISAExt] }
+          , armISAExt :: [ArmISAExt]
+          , armABI    :: ArmABI
+          }
         deriving (Read, Show, Eq)
 
 
@@ -61,7 +64,7 @@ data OS
         | OSHaiku
         deriving (Read, Show, Eq)
 
--- | ARM Instruction Set Architecture and Extensions
+-- | ARM Instruction Set Architecture, Extensions and ABI
 --
 data ArmISA
     = ARMv5
@@ -77,6 +80,11 @@ data ArmISAExt
     | IWMMX2
     deriving (Read, Show, Eq)
 
+data ArmABI
+    = SOFT
+    | SOFTFP
+    | HARD
+    deriving (Read, Show, Eq)
 
 target32Bit :: Platform -> Bool
 target32Bit p = platformWordSize p == 4

configure.ac

@@ -210,6 +210,20 @@ AC_CANONICAL_BUILD
 AC_CANONICAL_HOST
 AC_CANONICAL_TARGET
 
+# Testing ARM ABI
+# required for code generation (LLVM options)
+ARM_ABI=SOFT
+echo HOST: $host
+
+case $host in
+     arm*-*-linux-gnueabihf)
+     ARM_ABI=HARD
+     ;;
+     arm*-*-linux-gnueabi)
+     ARM_ABI=SOFTFP
+     ;;
+esac
+
 FPTOOLS_SET_PLATFORM_VARS
 
 # Verify that the installed (bootstrap) GHC is capable of generating