[project @ 2000-02-28 12:02:31 by sewardj]
Many changes to improve the quality and correctness of generated code, both for x86 and all-platforms. The intent is that the x86 NCG will now be good enough for general use. -- Add an almost-trivial Stix (generic) peephole optimiser, whose sole purpose is elide assignments to temporaries used only once, in the very next tree. This generates substantially better code for conditionals on all platforms. Enhance Stix constant folding to take advantage of the inlining. The inlining presents subsequent insn selection phases with more complex trees than would have previously been used to. This has shown up several bugs in the x86 insn selectors, now fixed. (assumptions that data size is Word, when could be Byte, assumptions that an operand will always be in a temp reg, etc) -- x86: Use the FLDZ and FLD1 insns. -- x86: spill FP registers with 80-bit loads/stores so that Intel's extra 16 bits of accuracy are not lost. If this isn't done, FP spills are not suitably transparent. Increase the number of spill words available to 2048. -- x86: give the register allocator more flexibility in choosing spill temporaries. -- x86, RegAllocInfo.regUsage: fix error for GST, and rewrite to make it clearer. -- Correctly track movements in the C stack pointer, and generate correct spill code for archs which spill against the stack pointer even when the stack pointer moves. Redo the x86 ccall mechanism to push args on the C stack in the normal way. Rather than have the spiller have to analyse code sequences to determine the current stack offset, the insn selectors communicate the current offset whenever it changes by inserting a DELTA pseudo-insn. Then the spiller only has to spot DELTAs. This means having a new native-code-generator monad (Stix.NatM) which carries both a UniqSupply and the current stack offset. -- Remove the asmPar/asmSeq ways of grouping insns together. In the presence of fixed registers, it is hard to demonstrate that insn selectors using asmPar always give correct code, and the extra complication doesn't help any. Also, directly construct code sequences using tree-based ordered lists (utils/OrdList.lhs) for linear-time appends, rather than the bizarrely complex method using fns and fn composition. -- Inline some hcats in printing of x86 address modes. -- Document more of the hidden assumptions which insn selection relies on, particular wrt addressing modes.
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