Commit 7b594a5d authored by dterei's avatar dterei

Remove registerised code for dead architectures: mips, ia64, alpha,

hppa1, m68k
parent 1c9af855
...@@ -958,9 +958,6 @@ cLoad platform expr rep ...@@ -958,9 +958,6 @@ cLoad platform expr rep
| otherwise | otherwise
= char '*' <> parens (cCast platform (machRepPtrCType rep) expr) = char '*' <> parens (cCast platform (machRepPtrCType rep) expr)
where -- On these platforms, unaligned loads are known to cause problems where -- On these platforms, unaligned loads are known to cause problems
bewareLoadStoreAlignment ArchAlpha = True
bewareLoadStoreAlignment ArchMipseb = True
bewareLoadStoreAlignment ArchMipsel = True
bewareLoadStoreAlignment (ArchARM {}) = True bewareLoadStoreAlignment (ArchARM {}) = True
bewareLoadStoreAlignment _ = False bewareLoadStoreAlignment _ = False
......
...@@ -211,12 +211,6 @@ nativeCodeGen dflags h us cmms ...@@ -211,12 +211,6 @@ nativeCodeGen dflags h us cmms
panic "nativeCodeGen: No NCG for ARM" panic "nativeCodeGen: No NCG for ARM"
ArchPPC_64 -> ArchPPC_64 ->
panic "nativeCodeGen: No NCG for PPC 64" panic "nativeCodeGen: No NCG for PPC 64"
ArchAlpha ->
panic "nativeCodeGen: No NCG for Alpha"
ArchMipseb ->
panic "nativeCodeGen: No NCG for mipseb"
ArchMipsel ->
panic "nativeCodeGen: No NCG for mipsel"
ArchUnknown -> ArchUnknown ->
panic "nativeCodeGen: No NCG for unknown arch" panic "nativeCodeGen: No NCG for unknown arch"
......
...@@ -113,9 +113,6 @@ trivColorable platform virtualRegSqueeze realRegSqueeze RcInteger conflicts excl ...@@ -113,9 +113,6 @@ trivColorable platform virtualRegSqueeze realRegSqueeze RcInteger conflicts excl
ArchSPARC -> 14 ArchSPARC -> 14
ArchPPC_64 -> panic "trivColorable ArchPPC_64" ArchPPC_64 -> panic "trivColorable ArchPPC_64"
ArchARM _ _ -> panic "trivColorable ArchARM" ArchARM _ _ -> panic "trivColorable ArchARM"
ArchAlpha -> panic "trivColorable ArchAlpha"
ArchMipseb -> panic "trivColorable ArchMipseb"
ArchMipsel -> panic "trivColorable ArchMipsel"
ArchUnknown -> panic "trivColorable ArchUnknown") ArchUnknown -> panic "trivColorable ArchUnknown")
, count2 <- accSqueeze (_ILIT(0)) cALLOCATABLE_REGS_INTEGER , count2 <- accSqueeze (_ILIT(0)) cALLOCATABLE_REGS_INTEGER
(virtualRegSqueeze RcInteger) (virtualRegSqueeze RcInteger)
...@@ -136,9 +133,6 @@ trivColorable platform virtualRegSqueeze realRegSqueeze RcFloat conflicts exclus ...@@ -136,9 +133,6 @@ trivColorable platform virtualRegSqueeze realRegSqueeze RcFloat conflicts exclus
ArchSPARC -> 22 ArchSPARC -> 22
ArchPPC_64 -> panic "trivColorable ArchPPC_64" ArchPPC_64 -> panic "trivColorable ArchPPC_64"
ArchARM _ _ -> panic "trivColorable ArchARM" ArchARM _ _ -> panic "trivColorable ArchARM"
ArchAlpha -> panic "trivColorable ArchAlpha"
ArchMipseb -> panic "trivColorable ArchMipseb"
ArchMipsel -> panic "trivColorable ArchMipsel"
ArchUnknown -> panic "trivColorable ArchUnknown") ArchUnknown -> panic "trivColorable ArchUnknown")
, count2 <- accSqueeze (_ILIT(0)) cALLOCATABLE_REGS_FLOAT , count2 <- accSqueeze (_ILIT(0)) cALLOCATABLE_REGS_FLOAT
(virtualRegSqueeze RcFloat) (virtualRegSqueeze RcFloat)
...@@ -159,9 +153,6 @@ trivColorable platform virtualRegSqueeze realRegSqueeze RcDouble conflicts exclu ...@@ -159,9 +153,6 @@ trivColorable platform virtualRegSqueeze realRegSqueeze RcDouble conflicts exclu
ArchSPARC -> 11 ArchSPARC -> 11
ArchPPC_64 -> panic "trivColorable ArchPPC_64" ArchPPC_64 -> panic "trivColorable ArchPPC_64"
ArchARM _ _ -> panic "trivColorable ArchARM" ArchARM _ _ -> panic "trivColorable ArchARM"
ArchAlpha -> panic "trivColorable ArchAlpha"
ArchMipseb -> panic "trivColorable ArchMipseb"
ArchMipsel -> panic "trivColorable ArchMipsel"
ArchUnknown -> panic "trivColorable ArchUnknown") ArchUnknown -> panic "trivColorable ArchUnknown")
, count2 <- accSqueeze (_ILIT(0)) cALLOCATABLE_REGS_DOUBLE , count2 <- accSqueeze (_ILIT(0)) cALLOCATABLE_REGS_DOUBLE
(virtualRegSqueeze RcDouble) (virtualRegSqueeze RcDouble)
...@@ -182,9 +173,6 @@ trivColorable platform virtualRegSqueeze realRegSqueeze RcDoubleSSE conflicts ex ...@@ -182,9 +173,6 @@ trivColorable platform virtualRegSqueeze realRegSqueeze RcDoubleSSE conflicts ex
ArchSPARC -> 0 ArchSPARC -> 0
ArchPPC_64 -> panic "trivColorable ArchPPC_64" ArchPPC_64 -> panic "trivColorable ArchPPC_64"
ArchARM _ _ -> panic "trivColorable ArchARM" ArchARM _ _ -> panic "trivColorable ArchARM"
ArchAlpha -> panic "trivColorable ArchAlpha"
ArchMipseb -> panic "trivColorable ArchMipseb"
ArchMipsel -> panic "trivColorable ArchMipsel"
ArchUnknown -> panic "trivColorable ArchUnknown") ArchUnknown -> panic "trivColorable ArchUnknown")
, count2 <- accSqueeze (_ILIT(0)) cALLOCATABLE_REGS_SSE , count2 <- accSqueeze (_ILIT(0)) cALLOCATABLE_REGS_SSE
(virtualRegSqueeze RcDoubleSSE) (virtualRegSqueeze RcDoubleSSE)
......
...@@ -74,8 +74,5 @@ maxSpillSlots platform ...@@ -74,8 +74,5 @@ maxSpillSlots platform
ArchSPARC -> SPARC.Instr.maxSpillSlots ArchSPARC -> SPARC.Instr.maxSpillSlots
ArchARM _ _ -> panic "maxSpillSlots ArchARM" ArchARM _ _ -> panic "maxSpillSlots ArchARM"
ArchPPC_64 -> panic "maxSpillSlots ArchPPC_64" ArchPPC_64 -> panic "maxSpillSlots ArchPPC_64"
ArchAlpha -> panic "maxSpillSlots ArchAlpha"
ArchMipseb -> panic "maxSpillSlots ArchMipseb"
ArchMipsel -> panic "maxSpillSlots ArchMipsel"
ArchUnknown -> panic "maxSpillSlots ArchUnknown" ArchUnknown -> panic "maxSpillSlots ArchUnknown"
...@@ -186,9 +186,6 @@ linearRegAlloc dflags first_id block_live sccs ...@@ -186,9 +186,6 @@ linearRegAlloc dflags first_id block_live sccs
ArchPPC -> linearRegAlloc' platform (frInitFreeRegs :: PPC.FreeRegs) first_id block_live sccs ArchPPC -> linearRegAlloc' platform (frInitFreeRegs :: PPC.FreeRegs) first_id block_live sccs
ArchARM _ _ -> panic "linearRegAlloc ArchARM" ArchARM _ _ -> panic "linearRegAlloc ArchARM"
ArchPPC_64 -> panic "linearRegAlloc ArchPPC_64" ArchPPC_64 -> panic "linearRegAlloc ArchPPC_64"
ArchAlpha -> panic "linearRegAlloc ArchAlpha"
ArchMipseb -> panic "linearRegAlloc ArchMipseb"
ArchMipsel -> panic "linearRegAlloc ArchMipsel"
ArchUnknown -> panic "linearRegAlloc ArchUnknown" ArchUnknown -> panic "linearRegAlloc ArchUnknown"
linearRegAlloc' linearRegAlloc'
......
...@@ -56,9 +56,6 @@ targetVirtualRegSqueeze platform ...@@ -56,9 +56,6 @@ targetVirtualRegSqueeze platform
ArchSPARC -> SPARC.virtualRegSqueeze ArchSPARC -> SPARC.virtualRegSqueeze
ArchPPC_64 -> panic "targetVirtualRegSqueeze ArchPPC_64" ArchPPC_64 -> panic "targetVirtualRegSqueeze ArchPPC_64"
ArchARM _ _ -> panic "targetVirtualRegSqueeze ArchARM" ArchARM _ _ -> panic "targetVirtualRegSqueeze ArchARM"
ArchAlpha -> panic "targetVirtualRegSqueeze ArchAlpha"
ArchMipseb -> panic "targetVirtualRegSqueeze ArchMipseb"
ArchMipsel -> panic "targetVirtualRegSqueeze ArchMipsel"
ArchUnknown -> panic "targetVirtualRegSqueeze ArchUnknown" ArchUnknown -> panic "targetVirtualRegSqueeze ArchUnknown"
targetRealRegSqueeze :: Platform -> RegClass -> RealReg -> FastInt targetRealRegSqueeze :: Platform -> RegClass -> RealReg -> FastInt
...@@ -70,9 +67,6 @@ targetRealRegSqueeze platform ...@@ -70,9 +67,6 @@ targetRealRegSqueeze platform
ArchSPARC -> SPARC.realRegSqueeze ArchSPARC -> SPARC.realRegSqueeze
ArchPPC_64 -> panic "targetRealRegSqueeze ArchPPC_64" ArchPPC_64 -> panic "targetRealRegSqueeze ArchPPC_64"
ArchARM _ _ -> panic "targetRealRegSqueeze ArchARM" ArchARM _ _ -> panic "targetRealRegSqueeze ArchARM"
ArchAlpha -> panic "targetRealRegSqueeze ArchAlpha"
ArchMipseb -> panic "targetRealRegSqueeze ArchMipseb"
ArchMipsel -> panic "targetRealRegSqueeze ArchMipsel"
ArchUnknown -> panic "targetRealRegSqueeze ArchUnknown" ArchUnknown -> panic "targetRealRegSqueeze ArchUnknown"
targetClassOfRealReg :: Platform -> RealReg -> RegClass targetClassOfRealReg :: Platform -> RealReg -> RegClass
...@@ -84,9 +78,6 @@ targetClassOfRealReg platform ...@@ -84,9 +78,6 @@ targetClassOfRealReg platform
ArchSPARC -> SPARC.classOfRealReg ArchSPARC -> SPARC.classOfRealReg
ArchPPC_64 -> panic "targetClassOfRealReg ArchPPC_64" ArchPPC_64 -> panic "targetClassOfRealReg ArchPPC_64"
ArchARM _ _ -> panic "targetClassOfRealReg ArchARM" ArchARM _ _ -> panic "targetClassOfRealReg ArchARM"
ArchAlpha -> panic "targetClassOfRealReg ArchAlpha"
ArchMipseb -> panic "targetClassOfRealReg ArchMipseb"
ArchMipsel -> panic "targetClassOfRealReg ArchMipsel"
ArchUnknown -> panic "targetClassOfRealReg ArchUnknown" ArchUnknown -> panic "targetClassOfRealReg ArchUnknown"
-- TODO: This should look at targetPlatform too -- TODO: This should look at targetPlatform too
...@@ -102,9 +93,6 @@ targetMkVirtualReg platform ...@@ -102,9 +93,6 @@ targetMkVirtualReg platform
ArchSPARC -> SPARC.mkVirtualReg ArchSPARC -> SPARC.mkVirtualReg
ArchPPC_64 -> panic "targetMkVirtualReg ArchPPC_64" ArchPPC_64 -> panic "targetMkVirtualReg ArchPPC_64"
ArchARM _ _ -> panic "targetMkVirtualReg ArchARM" ArchARM _ _ -> panic "targetMkVirtualReg ArchARM"
ArchAlpha -> panic "targetMkVirtualReg ArchAlpha"
ArchMipseb -> panic "targetMkVirtualReg ArchMipseb"
ArchMipsel -> panic "targetMkVirtualReg ArchMipsel"
ArchUnknown -> panic "targetMkVirtualReg ArchUnknown" ArchUnknown -> panic "targetMkVirtualReg ArchUnknown"
targetRegDotColor :: Platform -> RealReg -> SDoc targetRegDotColor :: Platform -> RealReg -> SDoc
...@@ -116,9 +104,6 @@ targetRegDotColor platform ...@@ -116,9 +104,6 @@ targetRegDotColor platform
ArchSPARC -> SPARC.regDotColor ArchSPARC -> SPARC.regDotColor
ArchPPC_64 -> panic "targetRegDotColor ArchPPC_64" ArchPPC_64 -> panic "targetRegDotColor ArchPPC_64"
ArchARM _ _ -> panic "targetRegDotColor ArchARM" ArchARM _ _ -> panic "targetRegDotColor ArchARM"
ArchAlpha -> panic "targetRegDotColor ArchAlpha"
ArchMipseb -> panic "targetRegDotColor ArchMipseb"
ArchMipsel -> panic "targetRegDotColor ArchMipsel"
ArchUnknown -> panic "targetRegDotColor ArchUnknown" ArchUnknown -> panic "targetRegDotColor ArchUnknown"
......
...@@ -42,9 +42,6 @@ data Arch ...@@ -42,9 +42,6 @@ data Arch
| ArchARM | ArchARM
{ armISA :: ArmISA { armISA :: ArmISA
, armISAExt :: [ArmISAExt] } , armISAExt :: [ArmISAExt] }
| ArchAlpha
| ArchMipseb
| ArchMipsel
deriving (Read, Show, Eq) deriving (Read, Show, Eq)
...@@ -86,9 +83,6 @@ target32Bit p = case platformArch p of ...@@ -86,9 +83,6 @@ target32Bit p = case platformArch p of
ArchPPC_64 -> False ArchPPC_64 -> False
ArchSPARC -> True ArchSPARC -> True
ArchARM _ _ -> True ArchARM _ _ -> True
ArchMipseb -> True
ArchMipsel -> True
ArchAlpha -> False
-- | This predicates tells us whether the OS supports ELF-like shared libraries. -- | This predicates tells us whether the OS supports ELF-like shared libraries.
......
...@@ -19,10 +19,8 @@ print OUTPUT "$NoOfSplitFiles\n"; ...@@ -19,10 +19,8 @@ print OUTPUT "$NoOfSplitFiles\n";
close(OUTPUT); close(OUTPUT);
exit(0); exit(0);
\end{code}
\begin{code}
sub split_asm_file { sub split_asm_file {
local($asm_file) = @_; local($asm_file) = @_;
my @pieces = (); my @pieces = ();
...@@ -223,13 +221,9 @@ sub process_asm_block { ...@@ -223,13 +221,9 @@ sub process_asm_block {
return(&process_asm_block_darwin($str)) return(&process_asm_block_darwin($str))
if $TargetPlatform =~ /-apple-darwin/m; if $TargetPlatform =~ /-apple-darwin/m;
return(&process_asm_block_m68k($str)) if $TargetPlatform =~ /^m68k-/m;
return(&process_asm_block_sparc($str)) if $TargetPlatform =~ /^sparc-/m; return(&process_asm_block_sparc($str)) if $TargetPlatform =~ /^sparc-/m;
return(&process_asm_block_iX86($str)) if $TargetPlatform =~ /^i[34]86-/m; return(&process_asm_block_iX86($str)) if $TargetPlatform =~ /^i[34]86-/m;
return(&process_asm_block_x86_64($str)) if $TargetPlatform =~ /^x86_64-/m; return(&process_asm_block_x86_64($str)) if $TargetPlatform =~ /^x86_64-/m;
return(&process_asm_block_alpha($str)) if $TargetPlatform =~ /^alpha-/m;
return(&process_asm_block_hppa($str)) if $TargetPlatform =~ /^hppa/m;
return(&process_asm_block_mips($str)) if $TargetPlatform =~ /^mips-/m;
return(&process_asm_block_powerpc_linux($str)) return(&process_asm_block_powerpc_linux($str))
if $TargetPlatform =~ /^powerpc-[^-]+-linux/m; if $TargetPlatform =~ /^powerpc-[^-]+-linux/m;
...@@ -276,82 +270,6 @@ sub process_asm_block_sparc { ...@@ -276,82 +270,6 @@ sub process_asm_block_sparc {
$str; $str;
} }
sub process_asm_block_m68k {
local($str) = @_;
# strip the marker
$str =~ s/(\.text\n\t\.even\n)\t\.globl\s+.*_?__stg_split_marker.*\n/$1/m;
$str =~ s/(\t\.even\n)\t\.globl\s+.*_?__stg_split_marker.*\n/$1/m;
# it seems prudent to stick on one of these:
$str = "\.text\n\t.even\n" . $str;
# remove/record any literal constants defined here
while ( $str =~ /((LC\d+):\n\t\.ascii.*\n)/m ) {
local($label) = $2;
local($body) = $1;
&tidy_up_and_die(1,"Local constant label $label already defined!\n")
if $LocalConstant{$label};
$LocalConstant{$label} = $body;
$str =~ s/LC\d+:\n\t\.ascii.*\n//m;
}
# inject definitions for any local constants now used herein
foreach $k (keys %LocalConstant) {
if ( $str =~ /\b$k\b/m ) {
$str = $LocalConstant{$k} . $str;
}
}
print STDERR "### STRIPPED BLOCK (m68k):\n$str" if $Dump_asm_splitting_info;
$str;
}
sub process_asm_block_alpha {
local($str) = @_;
# strip the marker
if ( $OptimiseC ) {
$str =~ s/_?__stg_split_marker.*:\n//m;
} else {
$str =~ s/(\t\.align .\n)\t\.globl\s+.*_?__stg_split_marker.*\n\t\.ent.*\n/$1/m;
}
# remove/record any literal constants defined here
while ( $str =~ /(\.rdata\n\t\.align \d\n)?(\$(C\d+):\n\t\..*\n)/m ) {
local($label) = $3;
local($body) = $2;
&tidy_up_and_die(1,"Local constant label $label already defined!\n")
if $LocalConstant{$label};
$LocalConstant{$label} = ".rdata\n\t.align 3\n" . $body . "\t.text\n";
$str =~ s/(\.rdata\n\t\.align \d\n)?\$C\d+:\n\t\..*\n//m;
}
# inject definitions for any local constants now used herein
foreach $k (keys %LocalConstant) {
if ( $str =~ /\$\b$k\b/m ) {
$str = $LocalConstant{$k} . $str;
}
}
# Slide the dummy direct return code into the vtbl .ent/.end block,
# to keep the label fixed if it's the last thing in a module, and
# to avoid having any anonymous text that the linker will complain about
$str =~ s/(\t\.end [A-Za-z0-9_]+)\n\t# nop/\tnop\n$1/gm;
print STDERR "### STRIPPED BLOCK (alpha):\n$str" if $Dump_asm_splitting_info;
$str;
}
sub process_asm_block_iX86 { sub process_asm_block_iX86 {
local($str) = @_; local($str) = @_;
...@@ -395,9 +313,7 @@ sub process_asm_block_iX86 { ...@@ -395,9 +313,7 @@ sub process_asm_block_iX86 {
$str; $str;
} }
\end{code}
\begin{code}
sub process_asm_block_x86_64 { sub process_asm_block_x86_64 {
local($str) = @_; local($str) = @_;
...@@ -433,107 +349,7 @@ sub process_asm_block_x86_64 { ...@@ -433,107 +349,7 @@ sub process_asm_block_x86_64 {
$str; $str;
} }
\end{code}
\begin{code}
sub process_asm_block_hppa {
local($str) = @_;
# strip the marker
$str =~ s/___stg_split_marker.*\n//m;
# remove/record any imports defined here
while ( $str =~ /^(\s+\.IMPORT\s.*\n)/m ) {
$Imports .= $1;
$str =~ s/^\s+\.IMPORT.*\n//m;
}
# remove/record any literal constants defined here
while ( $str =~ /^(\s+\.align.*\n(L\$C\d+)\n(\s.*\n)+); end literal\n/m ) {
local($label) = $2;
local($body) = $1;
local($prefix) = $`;
local($suffix) = $';
$label =~ s/\$/\\\$/gm;
&tidy_up_and_die(1,"Local constant label $label already defined!\n")
if $LocalConstant{$label};
$LocalConstant{$label} = "\t.SPACE \$TEXT\$\n\t.SUBSPA \$LIT\$\n\n" . $body;
$str = $prefix . $suffix;
}
# inject definitions for any local constants now used herein
foreach $k (keys %LocalConstant) {
if ( $str =~ /\b$k\b/m ) {
$str = $LocalConstant{$k} . $str;
}
}
# inject required imports for local exports in other chunks
foreach $k (keys %LocalExport) {
if ( $str =~ /\b$k\b/m && ! /EXPORT\s+$k\b/m ) {
$str = $LocalExport{$k} . $str;
}
}
# inject collected imports
$str = $Imports . $str;
print STDERR "### STRIPPED BLOCK (hppa):\n$str" if $Dump_asm_splitting_info;
$str;
}
\end{code}
\begin{code}
sub process_asm_block_mips {
local($str) = @_;
# strip the marker
if ( $OptimiseC ) {
$str =~ s/_?__stg_split_marker.*:\n//m;
} else {
$str =~ s/(\t\.align .\n)\t\.globl\s+.*_?__stg_split_marker.*\n\t\.ent.*\n/$1/m;
}
# remove/record any literal constants defined here
while ( $str =~ /(\t\.rdata\n\t\.align \d\n)?^(\$(LC\d+):\n(\t\.byte\t.*\n)+)/m ) {
local($label) = $3;
local($body) = $2;
&tidy_up_and_die(1,"Local constant label $label already defined!\n")
if $LocalConstant{$label};
$LocalConstant{$label} = "\t.rdata\n\t.align 2\n" . $body . "\t.text\n";
$str =~ s/(\t\.rdata\n\t\.align \d\n)?\$LC\d+:\n(\t\.byte\t.*\n)+//m;
}
# inject definitions for any local constants now used herein
foreach $k (keys %LocalConstant) {
if ( $str =~ /\$\b$k\b/m ) {
$str = $LocalConstant{$k} . $str;
}
}
# Slide the dummy direct return code into the vtbl .ent/.end block,
# to keep the label fixed if it's the last thing in a module, and
# to avoid having any anonymous text that the linker will complain about
$str =~ s/(\t\.end [A-Za-z0-9_]+)\n\t# nop/\tnop\n$1/gm;
$str .= $UNDEFINED_FUNS; # pin on gratuitiously-large amount of info
print STDERR "### STRIPPED BLOCK (mips):\n$str" if $Dump_asm_splitting_info;
$str;
}
\end{code}
\begin{code}
# The logic for both Darwin/PowerPC and Darwin/x86 ends up being the same. # The logic for both Darwin/PowerPC and Darwin/x86 ends up being the same.
sub process_asm_block_darwin { sub process_asm_block_darwin {
...@@ -579,9 +395,7 @@ sub process_asm_block_darwin { ...@@ -579,9 +395,7 @@ sub process_asm_block_darwin {
$str; $str;
} }
\end{code}
\begin{code}
sub process_asm_block_powerpc_linux { sub process_asm_block_powerpc_linux {
local($str) = @_; local($str) = @_;
...@@ -610,12 +424,11 @@ sub process_asm_block_powerpc_linux { ...@@ -610,12 +424,11 @@ sub process_asm_block_powerpc_linux {
$str; $str;
} }
\end{code}
\begin{code}
sub tidy_up_and_die { sub tidy_up_and_die {
local($return_val, $msg) = @_; local($return_val, $msg) = @_;
print STDERR $msg; print STDERR $msg;
exit (($return_val == 0) ? 0 : 1); exit (($return_val == 0) ? 0 : 1);
} }
\end{code} \end{code}
...@@ -38,26 +38,16 @@ ...@@ -38,26 +38,16 @@
* we want to know about the register mapping on the TARGET platform. * we want to know about the register mapping on the TARGET platform.
*/ */
#ifdef COMPILING_GHC #ifdef COMPILING_GHC
#define alpha_REGS alpha_TARGET_ARCH
#define hppa1_1_REGS hppa1_1_TARGET_ARCH
#define i386_REGS i386_TARGET_ARCH #define i386_REGS i386_TARGET_ARCH
#define x86_64_REGS x86_64_TARGET_ARCH #define x86_64_REGS x86_64_TARGET_ARCH
#define m68k_REGS m68k_TARGET_ARCH
#define mips_REGS (mipsel_TARGET_ARCH || mipseb_TARGET_ARCH)
#define powerpc_REGS (powerpc_TARGET_ARCH || powerpc64_TARGET_ARCH || rs6000_TARGET_ARCH) #define powerpc_REGS (powerpc_TARGET_ARCH || powerpc64_TARGET_ARCH || rs6000_TARGET_ARCH)
#define ia64_REGS ia64_TARGET_ARCH
#define sparc_REGS sparc_TARGET_ARCH #define sparc_REGS sparc_TARGET_ARCH
#define arm_REGS arm_TARGET_ARCH #define arm_REGS arm_TARGET_ARCH
#define darwin_REGS darwin_TARGET_OS #define darwin_REGS darwin_TARGET_OS
#else #else
#define alpha_REGS alpha_HOST_ARCH
#define hppa1_1_REGS hppa1_1_HOST_ARCH
#define i386_REGS i386_HOST_ARCH #define i386_REGS i386_HOST_ARCH
#define x86_64_REGS x86_64_HOST_ARCH #define x86_64_REGS x86_64_HOST_ARCH
#define m68k_REGS m68k_HOST_ARCH
#define mips_REGS (mipsel_HOST_ARCH || mipseb_HOST_ARCH)
#define powerpc_REGS (powerpc_HOST_ARCH || powerpc64_HOST_ARCH || rs6000_HOST_ARCH) #define powerpc_REGS (powerpc_HOST_ARCH || powerpc64_HOST_ARCH || rs6000_HOST_ARCH)
#define ia64_REGS ia64_HOST_ARCH
#define sparc_REGS sparc_HOST_ARCH #define sparc_REGS sparc_HOST_ARCH
#define arm_REGS arm_HOST_ARCH #define arm_REGS arm_HOST_ARCH
#define darwin_REGS darwin_HOST_OS #define darwin_REGS darwin_HOST_OS
...@@ -76,139 +66,6 @@ ...@@ -76,139 +66,6 @@
this code path is completely untested! -- EZY this code path is completely untested! -- EZY
-------------------------------------------------------------------------- */ -------------------------------------------------------------------------- */
/* -----------------------------------------------------------------------------
The DEC Alpha register mapping
Alpha registers
\tr{$9}--\tr{$14} are our ``prize'' callee-save registers.
\tr{$15} is the frame pointer, and \tr{$16}--\tr{$21} are argument
registers. (These are off-limits.) We can steal some of the \tr{$22}-and-up
caller-save registers provided we do the appropriate save/restore stuff.
\tr{$f2}--\tr{$f9} are some callee-save floating-point registers.
We cannot use \tr{$23} (aka t9), \tr{$24} (aka t10), \tr{$25} (aka
t11), \tr{$27} (aka pv), or \tr{$28} (aka at), because they are
occasionally required by the assembler to handle non-primitive
instructions (e.g. ldb, remq). Sigh!
Cheat sheet for GDB:
GDB here Main map
=== ==== ========
s5 $14 R1
t1 $2 R2
t2 $3 R3
t3 $4 R4
t4 $5 R5
t5 $6 R6
t6 $7 R7
t7 $8 R8
s0 $9 Sp
s2 $11 SpLim
s3 $12 Hp
t8 $22 NCG_reserved
t12 $27 NCG_reserved
-------------------------------------------------------------------------- */
#if alpha_REGS
# define REG(x) __asm__("$" #x)
# define CALLER_SAVES_R2
# define CALLER_SAVES_R3
# define CALLER_SAVES_R4
# define CALLER_SAVES_R5
# define CALLER_SAVES_R6
# define CALLER_SAVES_R7
# define CALLER_SAVES_R8
# define CALLER_SAVES_USER
# define REG_R1 14
# define REG_R2 2
# define REG_R3 3
# define REG_R4 4
# define REG_R5 5
# define REG_R6 6
# define REG_R7 7
# define REG_R8 8
# define REG_F1 f2
# define REG_F2 f3
# define REG_F3 f4
# define REG_F4 f5
# define REG_D1 f6
# define REG_D2 f7
# define REG_Sp 9
# define REG_SpLim 11
# define REG_Hp 12
# define NCG_Reserved_I1 22
# define NCG_Reserved_I2 27
# define NCG_Reserved_F1 f29
# define NCG_Reserved_F2 f30
#endif /* alpha_REGS */