Commit 7bec5cbf authored by simonmar's avatar simonmar
Browse files

[project @ 2005-04-04 15:51:45 by simonmar]

wibble
parent da5cbb63
......@@ -41,7 +41,6 @@ module MachRegs (
spRel,
#if alpha_TARGET_ARCH
allArgRegs,
fits8Bits,
fReg,
gp, pv, ra, sp, t9, t10, t11, t12, v0, f0, zeroh,
......
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