Commit 8e02c0a5 authored by Gabor Greif's avatar Gabor Greif 💬
Browse files

Fix typos

parent a7b08c05
......@@ -2,7 +2,7 @@
--
-- The register liveness determinator
--
-- (c) The University of Glasgow 2004
-- (c) The University of Glasgow 2004-2013
--
-----------------------------------------------------------------------------
module RegAlloc.Liveness (
......@@ -423,7 +423,7 @@ slurpReloadCoalesce live
, slotMap' <- addToUFM slotMap slot reg
= return (slotMap', Nothing)
-- add an edge betwen the this reg and the last one stored into the slot
-- add an edge between the this reg and the last one stored into the slot
| LiveInstr (RELOAD slot reg) _ <- li
= case lookupUFM slotMap slot of
Just reg2
......@@ -594,7 +594,7 @@ patchEraseLive patchF cmm
-- source and destination regs are the same
| r1 == r2 = True
-- desination reg is never used
-- destination reg is never used
| elementOfUniqSet r2 (liveBorn live)
, elementOfUniqSet r2 (liveDieRead live) || elementOfUniqSet r2 (liveDieWrite live)
= True
......
......@@ -2,7 +2,7 @@
--
-- Generating machine code (instruction selection)
--
-- (c) The University of Glasgow 1996-2004
-- (c) The University of Glasgow 1996-2013
--
-----------------------------------------------------------------------------
......@@ -538,7 +538,7 @@ move_final (v:vs) (a:az) offset
-- | Assign results returned from the call into their
-- desination regs.
-- destination regs.
--
assign_code :: Platform -> [LocalReg] -> OrdList Instr
......
......@@ -36,7 +36,7 @@ import Outputable
-- | Code to assign a 64 bit value to memory.
assignMem_I64Code
:: CmmExpr -- ^ expr producing the desination address
:: CmmExpr -- ^ expr producing the destination address
-> CmmExpr -- ^ expr producing the source value.
-> NatM InstrBlock
......
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