Commit bab9a72d authored by kgardas's avatar kgardas
Browse files

enhance ArchARM with ISA and ISA extensions

This patch enhances ArchARM with ARM ISA and ISA extensions details
as is suggested in the comment in Platform.hs file. The patch is needed
by future patch which will use ARM ISA information in order to pass
appropriate command-line option to the LLVM llc tool.
parent 2906db6c
......@@ -199,7 +199,7 @@ nativeCodeGen dflags h us cmms
,ncgExpandTop = map SPARC.CodeGen.Expand.expandTop
,ncgMakeFarBranches = id
}
ArchARM ->
ArchARM _ _ ->
panic "nativeCodeGen: No NCG for ARM"
ArchPPC_64 ->
panic "nativeCodeGen: No NCG for PPC 64"
......
......@@ -112,7 +112,7 @@ trivColorable platform virtualRegSqueeze realRegSqueeze RcInteger conflicts excl
ArchPPC -> 16
ArchSPARC -> 14
ArchPPC_64 -> panic "trivColorable ArchPPC_64"
ArchARM -> panic "trivColorable ArchARM"
ArchARM _ _ -> panic "trivColorable ArchARM"
ArchUnknown -> panic "trivColorable ArchUnknown")
, count2 <- accSqueeze (_ILIT(0)) cALLOCATABLE_REGS_INTEGER
(virtualRegSqueeze RcInteger)
......@@ -132,7 +132,7 @@ trivColorable platform virtualRegSqueeze realRegSqueeze RcFloat conflicts exclus
ArchPPC -> 0
ArchSPARC -> 22
ArchPPC_64 -> panic "trivColorable ArchPPC_64"
ArchARM -> panic "trivColorable ArchARM"
ArchARM _ _ -> panic "trivColorable ArchARM"
ArchUnknown -> panic "trivColorable ArchUnknown")
, count2 <- accSqueeze (_ILIT(0)) cALLOCATABLE_REGS_FLOAT
(virtualRegSqueeze RcFloat)
......@@ -152,7 +152,7 @@ trivColorable platform virtualRegSqueeze realRegSqueeze RcDouble conflicts exclu
ArchPPC -> 26
ArchSPARC -> 11
ArchPPC_64 -> panic "trivColorable ArchPPC_64"
ArchARM -> panic "trivColorable ArchARM"
ArchARM _ _ -> panic "trivColorable ArchARM"
ArchUnknown -> panic "trivColorable ArchUnknown")
, count2 <- accSqueeze (_ILIT(0)) cALLOCATABLE_REGS_DOUBLE
(virtualRegSqueeze RcDouble)
......@@ -172,7 +172,7 @@ trivColorable platform virtualRegSqueeze realRegSqueeze RcDoubleSSE conflicts ex
ArchPPC -> 0
ArchSPARC -> 0
ArchPPC_64 -> panic "trivColorable ArchPPC_64"
ArchARM -> panic "trivColorable ArchARM"
ArchARM _ _ -> panic "trivColorable ArchARM"
ArchUnknown -> panic "trivColorable ArchUnknown")
, count2 <- accSqueeze (_ILIT(0)) cALLOCATABLE_REGS_SSE
(virtualRegSqueeze RcDoubleSSE)
......
......@@ -65,7 +65,7 @@ maxSpillSlots platform
ArchX86_64 -> X86.Instr.maxSpillSlots
ArchPPC -> PPC.Instr.maxSpillSlots
ArchSPARC -> SPARC.Instr.maxSpillSlots
ArchARM -> panic "maxSpillSlots ArchARM"
ArchARM _ _ -> panic "maxSpillSlots ArchARM"
ArchPPC_64 -> panic "maxSpillSlots ArchPPC_64"
ArchUnknown -> panic "maxSpillSlots ArchUnknown"
......@@ -184,7 +184,7 @@ linearRegAlloc dflags first_id block_live sccs
ArchX86_64 -> linearRegAlloc' platform (frInitFreeRegs :: X86.FreeRegs) first_id block_live sccs
ArchSPARC -> linearRegAlloc' platform (frInitFreeRegs :: SPARC.FreeRegs) first_id block_live sccs
ArchPPC -> linearRegAlloc' platform (frInitFreeRegs :: PPC.FreeRegs) first_id block_live sccs
ArchARM -> panic "linearRegAlloc ArchARM"
ArchARM _ _ -> panic "linearRegAlloc ArchARM"
ArchPPC_64 -> panic "linearRegAlloc ArchPPC_64"
ArchUnknown -> panic "linearRegAlloc ArchUnknown"
......
......@@ -48,7 +48,7 @@ targetVirtualRegSqueeze platform
ArchPPC -> PPC.virtualRegSqueeze
ArchSPARC -> SPARC.virtualRegSqueeze
ArchPPC_64 -> panic "targetVirtualRegSqueeze ArchPPC_64"
ArchARM -> panic "targetVirtualRegSqueeze ArchARM"
ArchARM _ _ -> panic "targetVirtualRegSqueeze ArchARM"
ArchUnknown -> panic "targetVirtualRegSqueeze ArchUnknown"
targetRealRegSqueeze :: Platform -> RegClass -> RealReg -> FastInt
......@@ -59,7 +59,7 @@ targetRealRegSqueeze platform
ArchPPC -> PPC.realRegSqueeze
ArchSPARC -> SPARC.realRegSqueeze
ArchPPC_64 -> panic "targetRealRegSqueeze ArchPPC_64"
ArchARM -> panic "targetRealRegSqueeze ArchARM"
ArchARM _ _ -> panic "targetRealRegSqueeze ArchARM"
ArchUnknown -> panic "targetRealRegSqueeze ArchUnknown"
targetClassOfRealReg :: Platform -> RealReg -> RegClass
......@@ -70,7 +70,7 @@ targetClassOfRealReg platform
ArchPPC -> PPC.classOfRealReg
ArchSPARC -> SPARC.classOfRealReg
ArchPPC_64 -> panic "targetClassOfRealReg ArchPPC_64"
ArchARM -> panic "targetClassOfRealReg ArchARM"
ArchARM _ _ -> panic "targetClassOfRealReg ArchARM"
ArchUnknown -> panic "targetClassOfRealReg ArchUnknown"
-- TODO: This should look at targetPlatform too
......@@ -85,7 +85,7 @@ targetMkVirtualReg platform
ArchPPC -> PPC.mkVirtualReg
ArchSPARC -> SPARC.mkVirtualReg
ArchPPC_64 -> panic "targetMkVirtualReg ArchPPC_64"
ArchARM -> panic "targetMkVirtualReg ArchARM"
ArchARM _ _ -> panic "targetMkVirtualReg ArchARM"
ArchUnknown -> panic "targetMkVirtualReg ArchUnknown"
targetRegDotColor :: Platform -> RealReg -> SDoc
......@@ -96,7 +96,7 @@ targetRegDotColor platform
ArchPPC -> PPC.regDotColor
ArchSPARC -> SPARC.regDotColor
ArchPPC_64 -> panic "targetRegDotColor ArchPPC_64"
ArchARM -> panic "targetRegDotColor ArchARM"
ArchARM _ _ -> panic "targetRegDotColor ArchARM"
ArchUnknown -> panic "targetRegDotColor ArchUnknown"
......
......@@ -58,7 +58,7 @@ normalRegColors platform
ArchPPC -> panic "X86 normalRegColors ArchPPC"
ArchPPC_64 -> panic "X86 normalRegColors ArchPPC_64"
ArchSPARC -> panic "X86 normalRegColors ArchSPARC"
ArchARM -> panic "X86 normalRegColors ArchARM"
ArchARM _ _ -> panic "X86 normalRegColors ArchARM"
ArchUnknown -> panic "X86 normalRegColors ArchUnknown"
fpRegColors :: [(Reg,String)]
......
......@@ -7,6 +7,8 @@ module Platform (
Platform(..),
Arch(..),
OS(..),
ArmISA(..),
ArmISAExt(..),
defaultTargetPlatform,
target32Bit,
......@@ -40,6 +42,8 @@ data Arch
| ArchPPC_64
| ArchSPARC
| ArchARM
{ armISA :: ArmISA
, armISAExt :: [ArmISAExt] }
deriving (Show, Eq)
......@@ -55,6 +59,22 @@ data OS
| OSOpenBSD
deriving (Show, Eq)
-- | ARM Instruction Set Architecture and Extensions
--
data ArmISA
= ARMv5
| ARMv6
| ARMv7
deriving (Show, Eq)
data ArmISAExt
= VFPv2
| VFPv3
| VFPv3D16
| NEON
| IWMMX2
deriving (Show, Eq)
target32Bit :: Platform -> Bool
target32Bit p = case platformArch p of
......@@ -64,7 +84,7 @@ target32Bit p = case platformArch p of
ArchPPC -> True
ArchPPC_64 -> False
ArchSPARC -> True
ArchARM -> True
ArchARM _ _ -> True
-- | This predicates tells us whether the OS supports ELF-like shared libraries.
......@@ -98,7 +118,7 @@ defaultTargetArch = ArchPPC_64
#elif sparc_TARGET_ARCH
defaultTargetArch = ArchSPARC
#elif arm_TARGET_ARCH
defaultTargetArch = ArchARM
defaultTargetArch = ArchARM defaultTargetArmISA defaultTargetArmISAExt
#else
defaultTargetArch = ArchUnknown
#endif
......@@ -124,3 +144,22 @@ defaultTargetOS = OSOpenBSD
defaultTargetOS = OSUnknown
#endif
#if arm_TARGET_ARCH
defaultTargetArmISA :: ArmISA
#if defined(arm_HOST_ARCH_PRE_ARMv6)
defaultTargetArmISA = ARMv5
#elif defined(arm_HOST_ARCH_PRE_ARMv7)
defaultTargetArmISA = ARMv6
#else
defaultTargetArmISA = ARMv7
#endif
defaultTargetArmISAExt :: [ArmISAExt]
#if defined(arm_TARGET_ARCH) && !defined(arm_HOST_ARCH_PRE_ARMv7)
/* wild guess really, in case of ARMv7 we assume both VFPv3 and NEON presented
however this is not true for SoCs like NVidia Tegra2 and Marvell Dove */
defaultTargetArmISAExt = [VFPv3, NEON]
#else
defaultTargetArmISAExt = []
#endif
#endif /* arm_TARGET_ARCH */
libraries/random
get
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