1. 04 Feb, 2010 1 commit
    • Simon Marlow's avatar
      Implement SSE2 floating-point support in the x86 native code generator (#594) · 335b9f36
      Simon Marlow authored
      The new flag -msse2 enables code generation for SSE2 on x86.  It
      results in substantially faster floating-point performance; the main
      reason for doing this was that our x87 code generation is appallingly
      bad, and since we plan to drop -fvia-C soon, we need a way to generate
      half-decent floating-point code.
      
      The catch is that SSE2 is only available on CPUs that support it (P4+,
      AMD K8+).  We'll have to think hard about whether we should enable it
      by default for the libraries we ship.  In the meantime, at least
      -msse2 should be an acceptable replacement for "-fvia-C
      -optc-ffast-math -fexcess-precision".
      
      SSE2 also has the advantage of performing all operations at the
      correct precision, so floating-point results are consistent with other
      platforms.
      
      I also tweaked the x87 code generation a bit while I was here, now
      it's slighlty less bad than before.
      335b9f36
  2. 07 Jul, 2009 1 commit
  3. 18 May, 2009 1 commit
    • Ben.Lippmeier@anu.edu.au's avatar
      Split Reg into vreg/hreg and add register pairs · f9288086
      Ben.Lippmeier@anu.edu.au authored
       * The old Reg type is now split into VirtualReg and RealReg.
       * For the graph coloring allocator, the type of the register graph
         is now (Graph VirtualReg RegClass RealReg), which shows that it colors
         in nodes representing virtual regs with colors representing real regs.
         (as was intended)  
       * RealReg contains two contructors, RealRegSingle and RealRegPair,
         where RealRegPair is used to represent a SPARC double reg 
         constructed from two single precision FP regs. 
       * On SPARC we can now allocate double regs into an arbitrary register
         pair, instead of reserving some reg ranges to only hold float/double values. 
      f9288086
  4. 20 Apr, 2009 1 commit
  5. 30 Mar, 2009 1 commit
  6. 23 Feb, 2009 1 commit
  7. 16 Feb, 2009 1 commit
  8. 15 Feb, 2009 1 commit
    • Ben.Lippmeier@anu.edu.au's avatar
      NCG: Split up the native code generator into arch specific modules · b04a210e
      Ben.Lippmeier@anu.edu.au authored
        - nativeGen/Instruction defines a type class for a generic
          instruction set. Each of the instruction sets we have, 
          X86, PPC and SPARC are instances of it.
        
        - The register alloctors use this type class when they need
          info about a certain register or instruction, such as
          regUsage, mkSpillInstr, mkJumpInstr, patchRegs..
        
        - nativeGen/Platform defines some data types enumerating
          the architectures and operating systems supported by the 
          native code generator.
        
        - DynFlags now keeps track of the current build platform, and 
          the PositionIndependentCode module uses this to decide what
          to do instead of relying of #ifdefs.
        
        - It's not totally retargetable yet. Some info info about the
          build target is still hardwired, but I've tried to contain
          most of it to a single module, TargetRegs.
        
        - Moved the SPILL and RELOAD instructions into LiveInstr.
        
        - Reg and RegClass now have their own modules, and are shared
          across all architectures.
      b04a210e
  9. 05 Feb, 2009 1 commit
  10. 04 Feb, 2009 2 commits
  11. 03 Feb, 2009 1 commit