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Support 128-bit SIMD on AArch64 via LLVM backend

arata, mizuki requested to merge aratamizuki/ghc:simd-on-aarch64 into master

This MR extends SIMD support to AArch64 using ASIMD (NEON) as mentioned in #23410 (closed).

I assume that NEON registers can be treated like xmm (they are both 128-bit wide, and lower bits are shared with float and double).

LLVM's definition for GHC calling convention contains support for vector parameter passing via q4 and q5, so I use them.

Lastly, this MR is little tested. I enabled the two tests that use SIMD primitives in testsuite/, but I feel more tests should be added (possibly in another MR).

Edited by arata, mizuki

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