AArch64: fix signExtendReg W32 using SXTH instead of SXTW

Ian Duncanrequested to merge
semigroup/ghc:semigroup/aarch64/fix-sxtw into master

Tickets: #26978 and #27047 (closed).

From the commit message:

signExtendReg was using SXTH (sign-extend halfword, 16-bit) for W32-to-W64 sign extension. This should be SXTW (sign-extend word, 32-bit). SXTH only sign-extends the lower 16 bits, producing wrong results for 32-bit values whose bit 15 differs from bit 31.

Other fixes:

  • At sub-W64, code gen for MO_S_Mul2 should use W32 registers for SMULL source operands as per the ARM spec (SMULL Xd, Wn, Wm), and not W64.

  • Ensure signExtendReg uses the source width for the source operand in SXTW/SXTH/SXTB instructions. GNU as requires sxtw Xd,Wn (not sxtw Xd,Xn), while LLVM's integrated assembler on macOS is lenient.

  • Fix overflow flag computation for MO_S_Mul2. The overflow bit was exactly inverted for sub-W64 operands.

Edited by sheaf

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