Memory ordering

This page describes the memory ordering design in GHC.

Please update this page freely.

Background

There are various architectures about memory ordering (see here). GHC needs to correspond to each sort.

• Strong memory ordering:

  • X86, SPARC in TSO mode

• Weak memory ordering:

  • ARM, PowerPC

On weakly ordering machines, store-store and load-load instructions may be also reordered. So we need appropriate memory barriers.

Heap memory barriers

Here is the design note about heap memory barriers in GHC:

• Note [Heap memory barriers] in includes/stg/SMP.h

Related merge request and mails are here:

• !1128 (merged) (originally !734 (closed))
• Cmm Memory Model (Understanding #15449) at ghc-devs ML.

Related documents and articles

Here are some useful resources:

• The JSR-133 Cookbook for Compiler Writers
• LINUX KERNEL MEMORY BARRIERS
• Memory ordering
• LLVM Language Reference Manual, ‘cmpxchg’ Instruction