This page describes the memory ordering design in GHC.
Please update this page freely.
There are various architectures about memory ordering (see here). GHC needs to correspond to each sort.
Strong memory ordering:
- X86, SPARC in TSO mode
Weak memory ordering:
- ARM, PowerPC
On weakly ordering machines, store-store and load-load instructions may be also reordered. So we need appropriate memory barriers.
Heap memory barriers
Here is the design note about heap memory barriers in GHC:
Note [Heap memory barriers]in includes/stg/SMP.h
Related merge request and mails are here:
Related documents and articles
Here are some useful resources: