... | ... | @@ -55,7 +55,7 @@ |
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</td>
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<th><a href="https://gitlab.haskell.org//ghc/ghc/issues/8033">#8033</a></th>
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<th><a href="https://gitlab.haskell.org/ghc/ghc/issues/8033">#8033</a></th>
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<td>
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... | ... | @@ -81,7 +81,7 @@ |
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</td>
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<th>
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<a href="https://gitlab.haskell.org//ghc/ghc/issues/8033">add AVX register support to llvm calling convention</a>
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<a href="https://gitlab.haskell.org/ghc/ghc/issues/8033">add AVX register support to llvm calling convention</a>
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... | ... | @@ -133,7 +133,7 @@ |
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</td>
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<th><a href="https://gitlab.haskell.org//ghc/ghc/issues/10286">#10286</a></th>
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<th><a href="https://gitlab.haskell.org/ghc/ghc/issues/10286">#10286</a></th>
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<td>
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... | ... | @@ -159,7 +159,7 @@ |
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</td>
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<th>
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<a href="https://gitlab.haskell.org//ghc/ghc/issues/10286">native code generator: GHC crash at GHC.Prim SIMD vector</a>
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<a href="https://gitlab.haskell.org/ghc/ghc/issues/10286">native code generator: GHC crash at GHC.Prim SIMD vector</a>
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... | ... | @@ -260,7 +260,7 @@ |
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</td>
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<th><a href="https://gitlab.haskell.org//ghc/ghc/issues/3557">#3557</a></th>
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<th><a href="https://gitlab.haskell.org/ghc/ghc/issues/3557">#3557</a></th>
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<td>
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... | ... | @@ -286,7 +286,7 @@ |
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</td>
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<th>
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<a href="https://gitlab.haskell.org//ghc/ghc/issues/3557">CPU Vector instructions in GHC.Prim</a>
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<a href="https://gitlab.haskell.org/ghc/ghc/issues/3557">CPU Vector instructions in GHC.Prim</a>
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... | ... | @@ -338,7 +338,7 @@ |
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</td>
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<th><a href="https://gitlab.haskell.org//ghc/ghc/issues/7741">#7741</a></th>
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<th><a href="https://gitlab.haskell.org/ghc/ghc/issues/7741">#7741</a></th>
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<td>
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... | ... | @@ -364,7 +364,7 @@ |
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</td>
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<th>
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<a href="https://gitlab.haskell.org//ghc/ghc/issues/7741">Add SIMD support to x86/x86_64 NCG</a>
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<a href="https://gitlab.haskell.org/ghc/ghc/issues/7741">Add SIMD support to x86/x86_64 NCG</a>
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... | ... | @@ -416,7 +416,7 @@ |
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</td>
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<th><a href="https://gitlab.haskell.org//ghc/ghc/issues/10648">#10648</a></th>
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<th><a href="https://gitlab.haskell.org/ghc/ghc/issues/10648">#10648</a></th>
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<td>
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... | ... | @@ -442,7 +442,7 @@ |
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</td>
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<th>
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<a href="https://gitlab.haskell.org//ghc/ghc/issues/10648">Some 64-vector SIMD primitives are absolutely useless</a>
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<a href="https://gitlab.haskell.org/ghc/ghc/issues/10648">Some 64-vector SIMD primitives are absolutely useless</a>
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... | ... | @@ -494,7 +494,7 @@ |
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</td>
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<th><a href="https://gitlab.haskell.org//ghc/ghc/issues/13852">#13852</a></th>
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<th><a href="https://gitlab.haskell.org/ghc/ghc/issues/13852">#13852</a></th>
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<td>
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... | ... | @@ -520,7 +520,7 @@ |
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</td>
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<th>
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<a href="https://gitlab.haskell.org//ghc/ghc/issues/13852">Can we have more SIMD primops, corresponding to the untapped AVX etc. instructions?</a>
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<a href="https://gitlab.haskell.org/ghc/ghc/issues/13852">Can we have more SIMD primops, corresponding to the untapped AVX etc. instructions?</a>
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... | ... | @@ -572,7 +572,7 @@ |
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</td>
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<th><a href="https://gitlab.haskell.org//ghc/ghc/issues/12412">#12412</a></th>
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<th><a href="https://gitlab.haskell.org/ghc/ghc/issues/12412">#12412</a></th>
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<td>
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... | ... | @@ -598,7 +598,7 @@ |
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</td>
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<th>
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<a href="https://gitlab.haskell.org//ghc/ghc/issues/12412">SIMD things introduce a metric ton of known key things</a>
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<a href="https://gitlab.haskell.org/ghc/ghc/issues/12412">SIMD things introduce a metric ton of known key things</a>
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... | ... | @@ -655,7 +655,7 @@ |
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### Vector types
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Vectors of the following types are implemented: `Int32`, `Int64`, `Float`, and `Double`. These types and their associated primops can be found in [ \`GHC.Prim\`](https://downloads.haskell.org/~ghc/8.0.2/docs/html/libraries/ghc-prim-0.5.0.0/GHC-Prim.html#g:28).
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Vectors of the following types are implemented: `Int32`, `Int64`, `Float`, and `Double`. These types and their associated primops can be found in [\`GHC.Prim\`](https://downloads.haskell.org/~ghc/8.0.2/docs/html/libraries/ghc-prim-0.5.0.0/GHC-Prim.html#g:28).
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### Fixed and variable sized vectors
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... | ... | @@ -665,7 +665,7 @@ For each type, currently only one vector width is implemented, namely the width |
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## Code generators
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Only the LLVM code generator (i.e. `-fllvm`) is supported. However, work is [ afoot](https://github.com/Abhiroop/ghc-1/tree/wip/simd-ncg-support) to add support to the NCG as well.
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Only the LLVM code generator (i.e. `-fllvm`) is supported. However, work is [afoot](https://github.com/Abhiroop/ghc-1/tree/wip/simd-ncg-support) to add support to the NCG as well.
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## Cmm layer
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... | ... | @@ -703,4 +703,4 @@ The implementation does not attempt to align memory containing SIMD vectors. SIM |
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### Other resources of interest
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- This `ghc-devs` discussion: [ https://mail.haskell.org/pipermail/ghc-devs/2017-March/013899.html](https://mail.haskell.org/pipermail/ghc-devs/2017-March/013899.html) |
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- This `ghc-devs` discussion: [https://mail.haskell.org/pipermail/ghc-devs/2017-March/013899.html](https://mail.haskell.org/pipermail/ghc-devs/2017-March/013899.html) |