A few people have asked about support for the [RISC-V](https://riscv.org/) architecture. Currently GHC has no support for RISC-V. There are two ways it could be added: ## Via the LLVM backend This is likely the easiest. In fact, for a while I thought it would be trivial. Essentially all that is needed is: 1. map the STG registers onto the RISC-V machine registers (see `MachRegs.h`) 2. add a few cases to the build system 3. add support for GHC's calling convention into LLVM I have a (very old) [branch](https://gitlab.haskell.org/ghc/ghc/tree/wip/riscv) which does most of (1) and (2). It turns out that (3) is problematic on RISC-V due to how the backend is implemented. Whereas all other platforms supported by GHC use LLVM's Tablegen mechanism to represent the calling convention mapping (e.g. https://github.com/llvm-mirror/llvm/blob/40bcb88e84e914cfe09f5606987f1fd090ea0dd8/lib/Target/AArch64/AArch64CallingConvention.td#L262), the RISC-V backend took a much different direction (it's been a while since I have looked at this but I vaguely recall that the calling convention was rather tightly coupled with instruction selection; perhaps look at https://github.com/llvm-mirror/llvm/blob/40bcb88e84e914cfe09f5606987f1fd090ea0dd8/lib/Target/RISCV/RISCVISelLowering.cpp). ## Writing a native code generator Currently GHC has three NCG backends: x86, PowerPC, and SPARC. Adding a RISC-V backend would be a great project for someone.