Potential register allocation issue with multiple jump destinations at different vector widths
Looking at the code in `GHC.CmmToAsm.Reg.Liveness.liveness1`, I see:
```hs
live_from_branch = unionManyUniqSets (map targetLiveRegs targets)
```
What about then a situation where target1 expects live XMM1 but target2 expects live D1 (i.e. only the lower 64 bits of XMM1)? (I'm using STG register names as a shorthand, even though this is Cmm.)
Then this `unionManyUniqSets` could override XMM1 with D1, which could mean we accidentally drop the high 64 bits of XMM1 on the floor e.g. when spilling/reloading.
It's unclear to me how many other places in the code suffer from this problem.
issue