Commit 9fe7d20e authored by Ben Gamari's avatar Ben Gamari Committed by Ben Gamari

Ensure that we don't produce code for pre-ARMv7 without barriers

We are unable to produce load/store barriers for pre-ARMv7 targets.
Phab:D894 added dummy cases to SMP.h for these barriers to prevent the
build from failing under the assumption that there are no SMP-capable
devices of this vintage. However, #10433 points out that it is more
correct to simply set NOSMP for such targets.

Tested By: rwbarton

Test Plan: Validate

Reviewers: erikd, rwbarton, austin

Reviewed By: rwbarton

Subscribers: thomie

Differential Revision: https://phabricator.haskell.org/D1704

GHC Trac Issues: #10433
parent f0f63b39
......@@ -451,6 +451,8 @@ AC_DEFUN([GET_ARM_ISA],
[ARM_ABI="SOFTFP"]
)]
)
AC_SUBST(ARM_ISA)
])
......
......@@ -372,9 +372,7 @@ write_barrier(void) {
#elif sparc_HOST_ARCH
/* Sparc in TSO mode does not require store/store barriers. */
__asm__ __volatile__ ("" : : : "memory");
#elif arm_HOST_ARCH && defined(arm_HOST_ARCH_PRE_ARMv7)
__asm__ __volatile__ ("" : : : "memory");
#elif (arm_HOST_ARCH && !defined(arm_HOST_ARCH_PRE_ARMv7)) || aarch64_HOST_ARCH
#elif (arm_HOST_ARCH) || aarch64_HOST_ARCH
__asm__ __volatile__ ("dmb st" : : : "memory");
#else
#error memory barriers unimplemented on this architecture
......@@ -393,14 +391,7 @@ store_load_barrier(void) {
__asm__ __volatile__ ("sync" : : : "memory");
#elif sparc_HOST_ARCH
__asm__ __volatile__ ("membar #StoreLoad" : : : "memory");
#elif arm_HOST_ARCH && defined(arm_HOST_ARCH_PRE_ARMv7)
// TODO FIXME: This case probably isn't totally correct - just because we
// use a pre-ARMv7 toolchain (e.g. to target an old Android device), doesn't
// mean the binary won't run on a newer ARMv7 system - in which case it
// needs a proper barrier. So we should rethink this
// - Reid
__asm__ __volatile__ ("" : : : "memory");
#elif arm_HOST_ARCH && !defined(arm_HOST_ARCH_PRE_ARMv7)
#elif arm_HOST_ARCH
__asm__ __volatile__ ("dmb" : : : "memory");
#elif aarch64_HOST_ARCH
__asm__ __volatile__ ("dmb sy" : : : "memory");
......@@ -422,9 +413,7 @@ load_load_barrier(void) {
#elif sparc_HOST_ARCH
/* Sparc in TSO mode does not require load/load barriers. */
__asm__ __volatile__ ("" : : : "memory");
#elif arm_HOST_ARCH && defined(arm_HOST_ARCH_PRE_ARMv7)
__asm__ __volatile__ ("" : : : "memory");
#elif arm_HOST_ARCH && !defined(arm_HOST_ARCH_PRE_ARMv7)
#elif arm_HOST_ARCH
__asm__ __volatile__ ("dmb" : : : "memory");
#elif aarch64_HOST_ARCH
__asm__ __volatile__ ("dmb sy" : : : "memory");
......
......@@ -184,7 +184,12 @@ HaveLibDL = @HaveLibDL@
# ArchSupportsSMP should be set iff there is support for that arch in
# includes/stg/SMP.h
ArchSupportsSMP=$(strip $(patsubst $(TargetArch_CPP), YES, $(findstring $(TargetArch_CPP), i386 x86_64 sparc powerpc powerpc64 powerpc64le arm aarch64)))
ifeq "$(TargetArch_CPP)" "arm"
# We don't support load/store barriers pre-ARMv7. See #10433.
ArchSupportsSMP="$(if $(filter $(ARM_ISA),ARMv5 ARMv6),NO,YES)"
else
ArchSupportsSMP=$(strip $(patsubst $(TargetArch_CPP), YES, $(findstring $(TargetArch_CPP), i386 x86_64 sparc powerpc powerpc64 powerpc64le aarch64)))
endif
GhcWithSMP := $(strip $(if $(filter YESNO, $(ArchSupportsSMP)$(GhcUnregisterised)),YES,NO))
......
......@@ -158,3 +158,7 @@ CC_CLANG_BACKEND = @CC_CLANG_BACKEND@
# Is the stage0 compiler affected by Bug #9439?
GHC_LLVM_AFFECTED_BY_9439 = @GHC_LLVM_AFFECTED_BY_9439@
ifeq "$(TargetArch_CPP)" "arm"
ARM_ISA=@ARM_ISA@
endif
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