Commit edad0624 authored by Ian Lynagh's avatar Ian Lynagh

Fix unregisterised builds, and building on non-x86/amd64/powerpc

parent 5431ce37
......@@ -17,6 +17,10 @@ endif
SRC_CC_OPTS += -I. -I../rts
ifneq "$(GhcWithSMP)" "YES"
SRC_CC_OPTS += -DNOSMP
endif
#
# Header file built from the configure script's findings
#
......
......@@ -333,7 +333,7 @@ struct PartCapability_ {
/* No such thing as a MainCapability under THREADED_RTS - each thread must have
* its own Capability.
*/
#if IN_STG_CODE && !defined(THREADED_RTS)
#if IN_STG_CODE && !(defined(THREADED_RTS) && !defined(NOSMP))
extern W_ MainCapability[];
#endif
......@@ -349,7 +349,7 @@ extern W_ MainCapability[];
GLOBAL_REG_DECL(StgRegTable *,BaseReg,REG_Base)
#define ASSIGN_BaseReg(e) (BaseReg = (e))
#else
#ifdef THREADED_RTS
#if defined(THREADED_RTS) && !defined(NOSMP)
#error BaseReg must be in a register for THREADED_RTS
#endif
#define BaseReg (&((struct PartCapability_ *)MainCapability)->r)
......
......@@ -48,6 +48,9 @@ xchg(StgPtr p, StgWord w)
:"=r" (result)
:"r" (w), "r" (p)
);
#elif !defined(WITHSMP)
result = *p;
*p = w;
#else
#error xchg() unimplemented on this architecture
#endif
......@@ -81,6 +84,13 @@ cas(StgVolatilePtr p, StgWord o, StgWord n)
:"cc", "memory"
);
return result;
#elif !defined(WITHSMP)
StgWord result;
result = *p;
if (result == o) {
*p = n;
}
return result;
#else
#error cas() unimplemented on this architecture
#endif
......@@ -102,6 +112,8 @@ write_barrier(void) {
__asm__ __volatile__ ("" : : : "memory");
#elif powerpc_HOST_ARCH
__asm__ __volatile__ ("lwsync" : : : "memory");
#elif !defined(WITHSMP)
return;
#else
#error memory barriers unimplemented on this architecture
#endif
......@@ -117,7 +129,6 @@ write_barrier(void) {
INLINE_HEADER StgInfoTable *
lockClosure(StgClosure *p)
{
#if i386_HOST_ARCH || x86_64_HOST_ARCH || powerpc_HOST_ARCH
StgWord info;
do {
nat i = 0;
......@@ -127,21 +138,14 @@ lockClosure(StgClosure *p)
} while (++i < SPIN_COUNT);
yieldThread();
} while (1);
#else
ACQUIRE_SM_LOCK
#endif
}
INLINE_HEADER void
unlockClosure(StgClosure *p, StgInfoTable *info)
{
#if i386_HOST_ARCH || x86_64_HOST_ARCH || powerpc_HOST_ARCH
// This is a strictly ordered write, so we need a wb():
write_barrier();
p->header.info = info;
#else
RELEASE_SM_LOCK;
#endif
}
#else /* !THREADED_RTS */
......
......@@ -257,6 +257,14 @@ GhcWithJavaGen=NO
HaveLibDL = @HaveLibDL@
ArchSupportsSMP=$(strip $(patsubst $(HostArch_CPP), YES, $(findstring $(HostArch_CPP), i386 x86_64)))
ifeq "$(ArchSupportsSMP)" "YES"
GhcWithSMP=YES
else
GhcWithSMP=NO
endif
# Whether to include GHCi in the compiler. Depends on whether the RTS linker
# has support for this OS/ARCH combination.
......
......@@ -119,6 +119,11 @@ SRC_CC_OPTS += $(STANDARD_OPTS)
SRC_CC_OPTS += $(GhcRtsCcOpts)
SRC_HC_OPTS += $(GhcRtsHcOpts)
ifneq "$(GhcWithSMP)" "YES"
SRC_CC_OPTS += -DNOSMP
SRC_HC_OPTS += -optc-DNOSMP
endif
ifneq "$(DLLized)" "YES"
SRC_HC_OPTS += -static
endif
......
......@@ -418,7 +418,7 @@ usage_text[] = {
" -Dz DEBUG: stack squezing",
"",
#endif /* DEBUG */
#if defined(THREADED_RTS)
#if defined(THREADED_RTS) && !defined(NOSMP)
" -N<n> Use <n> OS threads (default: 1)",
" -qm Don't automatically migrate threads between CPUs",
" -qw Migrate a thread to the current CPU when it is woken up",
......@@ -1019,7 +1019,7 @@ error = rtsTrue;
}
break;
#ifdef THREADED_RTS
#if defined(THREADED_RTS) && !defined(NOSMP)
case 'N':
THREADED_BUILD_ONLY(
if (rts_argv[arg][2] != '\0') {
......
......@@ -85,11 +85,13 @@ register double fake_f9 __asm__("$f9");
StgRegTable * StgRun(StgFunPtr f, StgRegTable *basereg STG_UNUSED)
{
while (f) {
/* XXX Disabled due to RtsFlags[]/RtsFlags mismatch
IF_DEBUG(interpreter,
debugBelch("Jumping to ");
printPtr((P_)f); fflush(stdout);
debugBelch("\n");
);
*/
f = (StgFunPtr) (f)();
}
return (StgRegTable *)R1.p;
......
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