From 76549660c10f504228c57ed4c57cfbade4236ff1 Mon Sep 17 00:00:00 2001
From: Matthew Pickering <matthewtpickering@gmail.com>
Date: Mon, 30 Sep 2024 15:13:13 +0100
Subject: [PATCH] riscv: Avoid using csrr instruction to test for vector
registers
The csrr instruction isn't allowed in qemu user-mode, and raises an
illegal instruction error when it is encountered.
Therefore for now, we just hard-code that there is no support for vector
registers since the rest of the compiler doesn't support vector
registers for riscv.
Fixes #25312
(cherry picked from commit a49e66fcf26632b31991384193e9fc0f7d051adc)
---
rts/CheckVectorSupport.c | 14 +++++++++-----
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/rts/CheckVectorSupport.c b/rts/CheckVectorSupport.c
index a8eaed58aec..bf5d86f3826 100644
--- a/rts/CheckVectorSupport.c
+++ b/rts/CheckVectorSupport.c
@@ -65,12 +65,16 @@ int checkVectorSupport(void) {
*/
#elif defined(__riscv)
- unsigned long vlenb;
- asm volatile ("csrr %0, vlenb" : "=r" (vlenb));
+// csrr instruction nott allowed in user-mode qemu emulation of riscv
+// Backend doesn't yet support vector registers, so hard-coded to no vector support
+// for now.
+//
+// unsigned long vlenb;
+// asm volatile ("csrr %0, vlenb" : "=r" (vlenb));
// VLENB gives the length in bytes
- supports_V16 = vlenb >= 16;
- supports_V32 = vlenb >= 32;
- supports_V64 = vlenb >= 64;
+ supports_V16 = 0;
+ supports_V32 = 0;
+ supports_V64 = 0;
#else
// On other platforms, we conservatively return no vector support.
--
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