Commit c29bf984 authored by Colin Watson's avatar Colin Watson Committed by Austin Seipp

ghc: initial AArch64 patches

Signed-off-by: default avatarAustin Seipp <austin@well-typed.com>
parent a3831391
......@@ -197,6 +197,9 @@ AC_DEFUN([FPTOOLS_SET_HASKELL_PLATFORM_VARS],
GET_ARM_ISA()
test -z "[$]2" || eval "[$]2=\"ArchARM {armISA = \$ARM_ISA, armISAExt = \$ARM_ISA_EXT, armABI = \$ARM_ABI}\""
;;
aarch64)
test -z "[$]2" || eval "[$]2=ArchARM64"
;;
alpha)
test -z "[$]2" || eval "[$]2=ArchAlpha"
;;
......@@ -1854,6 +1857,9 @@ AC_MSG_CHECKING(for path to top of build tree)
# converts cpu from gnu to ghc naming, and assigns the result to $target_var
AC_DEFUN([GHC_CONVERT_CPU],[
case "$1" in
aarch64*)
$2="aarch64"
;;
alpha*)
$2="alpha"
;;
......
......@@ -166,6 +166,7 @@ nativeCodeGen dflags this_mod h us cmms
ArchPPC -> nCG' (ppcNcgImpl dflags)
ArchSPARC -> nCG' (sparcNcgImpl dflags)
ArchARM {} -> panic "nativeCodeGen: No NCG for ARM"
ArchARM64 -> panic "nativeCodeGen: No NCG for ARM64"
ArchPPC_64 -> panic "nativeCodeGen: No NCG for PPC 64"
ArchAlpha -> panic "nativeCodeGen: No NCG for Alpha"
ArchMipseb -> panic "nativeCodeGen: No NCG for mipseb"
......
......@@ -113,6 +113,7 @@ trivColorable platform virtualRegSqueeze realRegSqueeze RcInteger conflicts excl
ArchSPARC -> 14
ArchPPC_64 -> panic "trivColorable ArchPPC_64"
ArchARM _ _ _ -> panic "trivColorable ArchARM"
ArchARM64 -> panic "trivColorable ArchARM64"
ArchAlpha -> panic "trivColorable ArchAlpha"
ArchMipseb -> panic "trivColorable ArchMipseb"
ArchMipsel -> panic "trivColorable ArchMipsel"
......@@ -137,6 +138,7 @@ trivColorable platform virtualRegSqueeze realRegSqueeze RcFloat conflicts exclus
ArchSPARC -> 22
ArchPPC_64 -> panic "trivColorable ArchPPC_64"
ArchARM _ _ _ -> panic "trivColorable ArchARM"
ArchARM64 -> panic "trivColorable ArchARM64"
ArchAlpha -> panic "trivColorable ArchAlpha"
ArchMipseb -> panic "trivColorable ArchMipseb"
ArchMipsel -> panic "trivColorable ArchMipsel"
......@@ -161,6 +163,7 @@ trivColorable platform virtualRegSqueeze realRegSqueeze RcDouble conflicts exclu
ArchSPARC -> 11
ArchPPC_64 -> panic "trivColorable ArchPPC_64"
ArchARM _ _ _ -> panic "trivColorable ArchARM"
ArchARM64 -> panic "trivColorable ArchARM64"
ArchAlpha -> panic "trivColorable ArchAlpha"
ArchMipseb -> panic "trivColorable ArchMipseb"
ArchMipsel -> panic "trivColorable ArchMipsel"
......@@ -185,6 +188,7 @@ trivColorable platform virtualRegSqueeze realRegSqueeze RcDoubleSSE conflicts ex
ArchSPARC -> 0
ArchPPC_64 -> panic "trivColorable ArchPPC_64"
ArchARM _ _ _ -> panic "trivColorable ArchARM"
ArchARM64 -> panic "trivColorable ArchARM64"
ArchAlpha -> panic "trivColorable ArchAlpha"
ArchMipseb -> panic "trivColorable ArchMipseb"
ArchMipsel -> panic "trivColorable ArchMipsel"
......
......@@ -74,6 +74,7 @@ maxSpillSlots dflags
ArchPPC -> PPC.Instr.maxSpillSlots dflags
ArchSPARC -> SPARC.Instr.maxSpillSlots dflags
ArchARM _ _ _ -> panic "maxSpillSlots ArchARM"
ArchARM64 -> panic "maxSpillSlots ArchARM64"
ArchPPC_64 -> panic "maxSpillSlots ArchPPC_64"
ArchAlpha -> panic "maxSpillSlots ArchAlpha"
ArchMipseb -> panic "maxSpillSlots ArchMipseb"
......
......@@ -207,6 +207,7 @@ linearRegAlloc dflags first_id block_live sccs
ArchSPARC -> linearRegAlloc' dflags (frInitFreeRegs platform :: SPARC.FreeRegs) first_id block_live sccs
ArchPPC -> linearRegAlloc' dflags (frInitFreeRegs platform :: PPC.FreeRegs) first_id block_live sccs
ArchARM _ _ _ -> panic "linearRegAlloc ArchARM"
ArchARM64 -> panic "linearRegAlloc ArchARM64"
ArchPPC_64 -> panic "linearRegAlloc ArchPPC_64"
ArchAlpha -> panic "linearRegAlloc ArchAlpha"
ArchMipseb -> panic "linearRegAlloc ArchMipseb"
......
......@@ -54,6 +54,7 @@ targetVirtualRegSqueeze platform
ArchSPARC -> SPARC.virtualRegSqueeze
ArchPPC_64 -> panic "targetVirtualRegSqueeze ArchPPC_64"
ArchARM _ _ _ -> panic "targetVirtualRegSqueeze ArchARM"
ArchARM64 -> panic "targetVirtualRegSqueeze ArchARM64"
ArchAlpha -> panic "targetVirtualRegSqueeze ArchAlpha"
ArchMipseb -> panic "targetVirtualRegSqueeze ArchMipseb"
ArchMipsel -> panic "targetVirtualRegSqueeze ArchMipsel"
......@@ -70,6 +71,7 @@ targetRealRegSqueeze platform
ArchSPARC -> SPARC.realRegSqueeze
ArchPPC_64 -> panic "targetRealRegSqueeze ArchPPC_64"
ArchARM _ _ _ -> panic "targetRealRegSqueeze ArchARM"
ArchARM64 -> panic "targetRealRegSqueeze ArchARM64"
ArchAlpha -> panic "targetRealRegSqueeze ArchAlpha"
ArchMipseb -> panic "targetRealRegSqueeze ArchMipseb"
ArchMipsel -> panic "targetRealRegSqueeze ArchMipsel"
......@@ -85,6 +87,7 @@ targetClassOfRealReg platform
ArchSPARC -> SPARC.classOfRealReg
ArchPPC_64 -> panic "targetClassOfRealReg ArchPPC_64"
ArchARM _ _ _ -> panic "targetClassOfRealReg ArchARM"
ArchARM64 -> panic "targetClassOfRealReg ArchARM64"
ArchAlpha -> panic "targetClassOfRealReg ArchAlpha"
ArchMipseb -> panic "targetClassOfRealReg ArchMipseb"
ArchMipsel -> panic "targetClassOfRealReg ArchMipsel"
......@@ -100,6 +103,7 @@ targetMkVirtualReg platform
ArchSPARC -> SPARC.mkVirtualReg
ArchPPC_64 -> panic "targetMkVirtualReg ArchPPC_64"
ArchARM _ _ _ -> panic "targetMkVirtualReg ArchARM"
ArchARM64 -> panic "targetMkVirtualReg ArchARM64"
ArchAlpha -> panic "targetMkVirtualReg ArchAlpha"
ArchMipseb -> panic "targetMkVirtualReg ArchMipseb"
ArchMipsel -> panic "targetMkVirtualReg ArchMipsel"
......@@ -115,6 +119,7 @@ targetRegDotColor platform
ArchSPARC -> SPARC.regDotColor
ArchPPC_64 -> panic "targetRegDotColor ArchPPC_64"
ArchARM _ _ _ -> panic "targetRegDotColor ArchARM"
ArchARM64 -> panic "targetRegDotColor ArchARM64"
ArchAlpha -> panic "targetRegDotColor ArchAlpha"
ArchMipseb -> panic "targetRegDotColor ArchMipseb"
ArchMipsel -> panic "targetRegDotColor ArchMipsel"
......
......@@ -52,6 +52,7 @@ data Arch
, armISAExt :: [ArmISAExt]
, armABI :: ArmABI
}
| ArchARM64
| ArchAlpha
| ArchMipseb
| ArchMipsel
......
......@@ -38,6 +38,7 @@
#define MACHREGS_powerpc (powerpc_TARGET_ARCH || powerpc64_TARGET_ARCH || rs6000_TARGET_ARCH)
#define MACHREGS_sparc sparc_TARGET_ARCH
#define MACHREGS_arm arm_TARGET_ARCH
#define MACHREGS_aarch64 aarch64_TARGET_ARCH
#define MACHREGS_darwin darwin_TARGET_OS
#endif
......
/* -----------------------------------------------------------------------------
*
* (c) The GHC Team, 1998-2011
* (c) The GHC Team, 1998-2014
*
* Registers used in STG code. Might or might not correspond to
* actual machine registers.
......@@ -531,6 +531,61 @@
#define REG_D2 d11
#endif
/* -----------------------------------------------------------------------------
The ARMv8/AArch64 ABI register mapping
The AArch64 provides 31 64-bit general purpose registers
and 32 128-bit SIMD/floating point registers.
General purpose registers (see Chapter 5.1.1 in ARM IHI 0055B)
Register | Special | Role in the procedure call standard
---------+---------+------------------------------------
SP | | The Stack Pointer
r30 | LR | The Link Register
r29 | FP | The Frame Pointer
r19-r28 | | Callee-saved registers
r18 | | The Platform Register, if needed;
| | or temporary register
r17 | IP1 | The second intra-procedure-call temporary register
r16 | IP0 | The first intra-procedure-call scratch register
r9-r15 | | Temporary registers
r8 | | Indirect result location register
r0-r7 | | Parameter/result registers
FPU/SIMD registers
s/d/q/v0-v7 Argument / result/ scratch registers
s/d/q/v8-v15 callee-saved registers (must be preserved across subrutine calls,
but only bottom 64-bit value needs to be preserved)
s/d/q/v16-v31 temporary registers
----------------------------------------------------------------------------- */
#elif MACHREGS_aarch64
#define REG(x) __asm__(#x)
#define REG_Base r19
#define REG_Sp r20
#define REG_Hp r21
#define REG_R1 r22
#define REG_R2 r23
#define REG_R3 r24
#define REG_R4 r25
#define REG_R5 r26
#define REG_R6 r27
#define REG_SpLim r28
#define REG_F1 s8
#define REG_F2 s9
#define REG_F3 s10
#define REG_F4 s11
#define REG_D1 d12
#define REG_D2 d13
#else
#error Cannot find platform to give register info for
......
......@@ -748,4 +748,70 @@ StgRun(StgFunPtr f, StgRegTable *basereg) {
}
#endif
#ifdef aarch64_HOST_ARCH
StgRegTable *
StgRun(StgFunPtr f, StgRegTable *basereg) {
StgRegTable * r;
__asm__ volatile (
/*
* save callee-saves registers on behalf of the STG code.
*/
"stp x19, x20, [sp, #-16]!\n\t"
"stp x21, x22, [sp, #-16]!\n\t"
"stp x23, x24, [sp, #-16]!\n\t"
"stp x25, x26, [sp, #-16]!\n\t"
"stp x27, x28, [sp, #-16]!\n\t"
"stp ip0, ip1, [sp, #-16]!\n\t"
"str lr, [sp, #-8]!\n\t"
/*
* allocate some space for Stg machine's temporary storage.
* Note: RESERVER_C_STACK_BYTES has to be a round number here or
* the assembler can't assemble it.
*/
"str lr, [sp, %3]"
/* "sub sp, sp, %3\n\t" */
/*
* Set BaseReg
*/
"mov x19, %2\n\t"
/*
* Jump to function argument.
*/
"bx %1\n\t"
".globl " STG_RETURN "\n\t"
".type " STG_RETURN ", %%function\n"
STG_RETURN ":\n\t"
/*
* Free the space we allocated
*/
"ldr lr, [sp], %3\n\t"
/* "add sp, sp, %3\n\t" */
/*
* Return the new register table, taking it from Stg's R1 (ARM64's R22).
*/
"mov %0, x22\n\t"
/*
* restore callee-saves registers.
*/
"ldr lr, [sp], #8\n\t"
"ldp ip0, ip1, [sp], #16\n\t"
"ldp x27, x28, [sp], #16\n\t"
"ldp x25, x26, [sp], #16\n\t"
"ldp x23, x24, [sp], #16\n\t"
"ldp x21, x22, [sp], #16\n\t"
"ldp x19, x20, [sp], #16\n\t"
: "=r" (r)
: "r" (f), "r" (basereg), "i" (RESERVED_C_STACK_BYTES)
: "%x19", "%x20", "%x21", "%x22", "%x23", "%x24", "%x25", "%x26", "%x27", "%x28",
"%ip0", "%ip1", "%lr"
);
return r;
}
#endif
#endif /* !USE_MINIINTERPRETER */
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