Commit eaaa38ba authored by Sergei Trofimovich's avatar Sergei Trofimovich

includes/stg/SMP.h: implement simple load_/store_load_barrier on armv6 and older

Assuming there is no real SMP systems on these CPUs
I've added only compiler barrier (otherwise write_barrier
and friends need to be fixed as well).

Patch also fixes build breakage reported in #10244.
Signed-off-by: default avatarSergei Trofimovich <siarheit@google.com>

Reviewers: rwbarton, nomeata, austin

Reviewed By: nomeata, austin

Subscribers: bgamari, thomie

Differential Revision: https://phabricator.haskell.org/D894

GHC Trac Issues: #10244
parent 228ddb95
......@@ -373,6 +373,8 @@ store_load_barrier(void) {
__asm__ __volatile__ ("sync" : : : "memory");
#elif sparc_HOST_ARCH
__asm__ __volatile__ ("membar #StoreLoad" : : : "memory");
#elif arm_HOST_ARCH && defined(arm_HOST_ARCH_PRE_ARMv7)
__asm__ __volatile__ ("" : : : "memory");
#elif arm_HOST_ARCH && !defined(arm_HOST_ARCH_PRE_ARMv7)
__asm__ __volatile__ ("dmb" : : : "memory");
#elif aarch64_HOST_ARCH
......@@ -395,6 +397,8 @@ load_load_barrier(void) {
#elif sparc_HOST_ARCH
/* Sparc in TSO mode does not require load/load barriers. */
__asm__ __volatile__ ("" : : : "memory");
#elif arm_HOST_ARCH && defined(arm_HOST_ARCH_PRE_ARMv7)
__asm__ __volatile__ ("" : : : "memory");
#elif arm_HOST_ARCH && !defined(arm_HOST_ARCH_PRE_ARMv7)
__asm__ __volatile__ ("dmb" : : : "memory");
#elif aarch64_HOST_ARCH
......
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