Commit f5f4f5ef authored by Andreas Schwab's avatar Andreas Schwab

Implement riscv64 LLVM backend

This patch adds support for the riscv64 architecture for the LLVM code
generator.
parent 8f1974f6
Pipeline #26532 failed with stages
in 319 minutes and 45 seconds
......@@ -204,6 +204,9 @@ AC_DEFUN([FPTOOLS_SET_HASKELL_PLATFORM_VARS],
powerpc64le)
test -z "[$]2" || eval "[$]2=\"ArchPPC_64 ELF_V2\""
;;
riscv64)
test -z "[$]2" || eval "[$]2=ArchRISCV64"
;;
s390x)
test -z "[$]2" || eval "[$]2=ArchS390X"
;;
......@@ -229,7 +232,7 @@ AC_DEFUN([FPTOOLS_SET_HASKELL_PLATFORM_VARS],
mipsel)
test -z "[$]2" || eval "[$]2=ArchMipsel"
;;
hppa|hppa1_1|ia64|m68k|nios2|riscv32|riscv64|rs6000|s390|sh4|vax)
hppa|hppa1_1|ia64|m68k|nios2|riscv32|rs6000|s390|sh4|vax)
test -z "[$]2" || eval "[$]2=ArchUnknown"
;;
*)
......
......@@ -165,6 +165,7 @@ nativeCodeGen dflags this_mod modLoc h us cmms
ArchSPARC -> nCG' (SPARC.ncgSPARC config)
ArchSPARC64 -> panic "nativeCodeGen: No NCG for SPARC64"
ArchS390X -> panic "nativeCodeGen: No NCG for S390X"
ArchRISCV64 -> panic "nativeCodeGen: No NCG for RISCV64"
ArchARM {} -> panic "nativeCodeGen: No NCG for ARM"
ArchARM64 -> panic "nativeCodeGen: No NCG for ARM64"
ArchAlpha -> panic "nativeCodeGen: No NCG for Alpha"
......
......@@ -119,6 +119,7 @@ trivColorable platform virtualRegSqueeze realRegSqueeze RcInteger conflicts excl
ArchAlpha -> panic "trivColorable ArchAlpha"
ArchMipseb -> panic "trivColorable ArchMipseb"
ArchMipsel -> panic "trivColorable ArchMipsel"
ArchRISCV64 -> panic "trivColorable ArchRISCV64"
ArchS390X -> panic "trivColorable ArchS390X"
ArchJavaScript-> panic "trivColorable ArchJavaScript"
ArchUnknown -> panic "trivColorable ArchUnknown")
......@@ -150,6 +151,7 @@ trivColorable platform virtualRegSqueeze realRegSqueeze RcFloat conflicts exclus
ArchAlpha -> panic "trivColorable ArchAlpha"
ArchMipseb -> panic "trivColorable ArchMipseb"
ArchMipsel -> panic "trivColorable ArchMipsel"
ArchRISCV64 -> panic "trivColorable ArchRISCV64"
ArchS390X -> panic "trivColorable ArchS390X"
ArchJavaScript-> panic "trivColorable ArchJavaScript"
ArchUnknown -> panic "trivColorable ArchUnknown")
......@@ -183,6 +185,7 @@ trivColorable platform virtualRegSqueeze realRegSqueeze RcDouble conflicts exclu
ArchAlpha -> panic "trivColorable ArchAlpha"
ArchMipseb -> panic "trivColorable ArchMipseb"
ArchMipsel -> panic "trivColorable ArchMipsel"
ArchRISCV64 -> panic "trivColorable ArchRISCV64"
ArchS390X -> panic "trivColorable ArchS390X"
ArchJavaScript-> panic "trivColorable ArchJavaScript"
ArchUnknown -> panic "trivColorable ArchUnknown")
......
......@@ -218,6 +218,7 @@ linearRegAlloc config entry_ids block_live sccs
= case platformArch platform of
ArchX86 -> go $ (frInitFreeRegs platform :: X86.FreeRegs)
ArchX86_64 -> go $ (frInitFreeRegs platform :: X86_64.FreeRegs)
ArchRISCV64 -> panic "linearRegAlloc ArchRISCV64"
ArchS390X -> panic "linearRegAlloc ArchS390X"
ArchSPARC -> go $ (frInitFreeRegs platform :: SPARC.FreeRegs)
ArchSPARC64 -> panic "linearRegAlloc ArchSPARC64"
......
......@@ -74,6 +74,7 @@ maxSpillSlots config = case platformArch (ncgPlatform config) of
ArchX86 -> X86.Instr.maxSpillSlots config
ArchX86_64 -> X86.Instr.maxSpillSlots config
ArchPPC -> PPC.Instr.maxSpillSlots config
ArchRISCV64 -> panic "maxSpillSlots ArchRISCV64"
ArchS390X -> panic "maxSpillSlots ArchS390X"
ArchSPARC -> SPARC.Instr.maxSpillSlots config
ArchSPARC64 -> panic "maxSpillSlots ArchSPARC64"
......
......@@ -43,6 +43,7 @@ targetVirtualRegSqueeze platform
ArchX86 -> X86.virtualRegSqueeze
ArchX86_64 -> X86.virtualRegSqueeze
ArchPPC -> PPC.virtualRegSqueeze
ArchRISCV64 -> panic "targetVirtualRegSqueeze ArchRISCV64"
ArchS390X -> panic "targetVirtualRegSqueeze ArchS390X"
ArchSPARC -> SPARC.virtualRegSqueeze
ArchSPARC64 -> panic "targetVirtualRegSqueeze ArchSPARC64"
......@@ -62,6 +63,7 @@ targetRealRegSqueeze platform
ArchX86 -> X86.realRegSqueeze
ArchX86_64 -> X86.realRegSqueeze
ArchPPC -> PPC.realRegSqueeze
ArchRISCV64 -> panic "targetRealRegSqueeze ArchRISCV64"
ArchS390X -> panic "targetRealRegSqueeze ArchS390X"
ArchSPARC -> SPARC.realRegSqueeze
ArchSPARC64 -> panic "targetRealRegSqueeze ArchSPARC64"
......@@ -80,6 +82,7 @@ targetClassOfRealReg platform
ArchX86 -> X86.classOfRealReg platform
ArchX86_64 -> X86.classOfRealReg platform
ArchPPC -> PPC.classOfRealReg
ArchRISCV64 -> panic "targetClassOfRealReg ArchRISCV64"
ArchS390X -> panic "targetClassOfRealReg ArchS390X"
ArchSPARC -> SPARC.classOfRealReg
ArchSPARC64 -> panic "targetClassOfRealReg ArchSPARC64"
......@@ -98,6 +101,7 @@ targetMkVirtualReg platform
ArchX86 -> X86.mkVirtualReg
ArchX86_64 -> X86.mkVirtualReg
ArchPPC -> PPC.mkVirtualReg
ArchRISCV64 -> panic "targetMkVirtualReg ArchRISCV64"
ArchS390X -> panic "targetMkVirtualReg ArchS390X"
ArchSPARC -> SPARC.mkVirtualReg
ArchSPARC64 -> panic "targetMkVirtualReg ArchSPARC64"
......@@ -116,6 +120,7 @@ targetRegDotColor platform
ArchX86 -> X86.regDotColor platform
ArchX86_64 -> X86.regDotColor platform
ArchPPC -> PPC.regDotColor
ArchRISCV64 -> panic "targetRegDotColor ArchRISCV64"
ArchS390X -> panic "targetRegDotColor ArchS390X"
ArchSPARC -> SPARC.regDotColor
ArchSPARC64 -> panic "targetRegDotColor ArchSPARC64"
......
{-# LANGUAGE CPP #-}
module GHC.Platform.RISCV64 where
import GHC.Prelude
#define MACHREGS_NO_REGS 0
#define MACHREGS_riscv64 1
#include "../../../includes/CodeGen.Platform.hs"
......@@ -12,6 +12,7 @@ import GHC.Platform.Reg
import qualified GHC.Platform.ARM as ARM
import qualified GHC.Platform.ARM64 as ARM64
import qualified GHC.Platform.PPC as PPC
import qualified GHC.Platform.RISCV64 as RISCV64
import qualified GHC.Platform.S390X as S390X
import qualified GHC.Platform.SPARC as SPARC
import qualified GHC.Platform.X86 as X86
......@@ -28,6 +29,7 @@ callerSaves platform
= case platformArch platform of
ArchX86 -> X86.callerSaves
ArchX86_64 -> X86_64.callerSaves
ArchRISCV64 -> RISCV64.callerSaves
ArchS390X -> S390X.callerSaves
ArchSPARC -> SPARC.callerSaves
ArchARM {} -> ARM.callerSaves
......@@ -50,6 +52,7 @@ activeStgRegs platform
= case platformArch platform of
ArchX86 -> X86.activeStgRegs
ArchX86_64 -> X86_64.activeStgRegs
ArchRISCV64 -> RISCV64.activeStgRegs
ArchS390X -> S390X.activeStgRegs
ArchSPARC -> SPARC.activeStgRegs
ArchARM {} -> ARM.activeStgRegs
......@@ -67,6 +70,7 @@ haveRegBase platform
= case platformArch platform of
ArchX86 -> X86.haveRegBase
ArchX86_64 -> X86_64.haveRegBase
ArchRISCV64 -> RISCV64.haveRegBase
ArchS390X -> S390X.haveRegBase
ArchSPARC -> SPARC.haveRegBase
ArchARM {} -> ARM.haveRegBase
......@@ -84,6 +88,7 @@ globalRegMaybe platform
= case platformArch platform of
ArchX86 -> X86.globalRegMaybe
ArchX86_64 -> X86_64.globalRegMaybe
ArchRISCV64 -> RISCV64.globalRegMaybe
ArchS390X -> S390X.globalRegMaybe
ArchSPARC -> SPARC.globalRegMaybe
ArchARM {} -> ARM.globalRegMaybe
......@@ -101,6 +106,7 @@ freeReg platform
= case platformArch platform of
ArchX86 -> X86.freeReg
ArchX86_64 -> X86_64.freeReg
ArchRISCV64 -> RISCV64.freeReg
ArchS390X -> S390X.freeReg
ArchSPARC -> SPARC.freeReg
ArchARM {} -> ARM.freeReg
......
......@@ -268,6 +268,7 @@ Library
GHC.Platform.ARM64
GHC.Platform.NoRegs
GHC.Platform.PPC
GHC.Platform.RISCV64
GHC.Platform.S390X
GHC.Platform.SPARC
GHC.Platform.X86
......
......@@ -281,7 +281,7 @@ dnl --------------------------------------------------------------
AC_MSG_CHECKING(whether target supports a registerised ABI)
case "$TargetArch" in
i386|x86_64|powerpc|powerpc64|powerpc64le|s390x|arm|aarch64)
i386|x86_64|powerpc|powerpc64|powerpc64le|riscv64|s390x|arm|aarch64)
UnregisterisedDefault=NO
AC_MSG_RESULT([yes])
;;
......@@ -316,7 +316,7 @@ AC_MSG_CHECKING(whether target supports tables next to code)
case "$Unregisterised" in
NO)
case "$TargetArch" in
ia64|powerpc64|powerpc64le|s390x)
ia64|powerpc64|powerpc64le|riscv64|s390x)
TablesNextToCodeDefault=NO
AC_MSG_RESULT([no])
;;
......@@ -345,7 +345,7 @@ AC_SUBST(TablesNextToCode)
dnl ** Does target have runtime linker support?
dnl --------------------------------------------------------------
case "$target" in
powerpc64-*|powerpc64le-*|powerpc-ibm-aix*|s390x-ibm-linux)
powerpc64-*|powerpc64le-*|powerpc-ibm-aix*|riscv64-*|s390x-ibm-linux)
TargetHasRTSLinker=NO
;;
*)
......
......@@ -70,7 +70,7 @@ targetSupportsSMP :: Action Bool
targetSupportsSMP = do
unreg <- flag GhcUnregisterised
armVer <- targetArmVersion
goodArch <- anyTargetArch ["i386", "x86_64", "sparc", "powerpc", "arm", "aarch64", "s390x"]
goodArch <- anyTargetArch ["i386", "x86_64", "sparc", "powerpc", "arm", "aarch64", "s390x", "riscv64"]
if -- The THREADED_RTS requires `BaseReg` to be in a register and the
-- Unregisterised mode doesn't allow that.
| unreg -> return False
......
......@@ -380,6 +380,74 @@ import GHC.Platform.Reg
# define f14 30
# define f15 31
#elif defined(MACHREGS_riscv64)
# define zero 0
# define ra 1
# define sp 2
# define gp 3
# define tp 4
# define t0 5
# define t1 6
# define t2 7
# define s0 8
# define s1 9
# define a0 10
# define a1 11
# define a2 12
# define a3 13
# define a4 14
# define a5 15
# define a6 16
# define a7 17
# define s2 18
# define s3 19
# define s4 20
# define s5 21
# define s6 22
# define s7 23
# define s8 24
# define s9 25
# define s10 26
# define s11 27
# define t3 28
# define t4 29
# define t5 30
# define t6 31
# define ft0 32
# define ft1 33
# define ft2 34
# define ft3 35
# define ft4 36
# define ft5 37
# define ft6 38
# define ft7 39
# define fs0 40
# define fs1 41
# define fa0 42
# define fa1 43
# define fa2 44
# define fa3 45
# define fa4 46
# define fa5 47
# define fa6 48
# define fa7 49
# define fs2 50
# define fs3 51
# define fs4 52
# define fs5 53
# define fs6 54
# define fs7 55
# define fs8 56
# define fs9 57
# define fs10 58
# define fs11 59
# define ft8 60
# define ft9 61
# define ft10 62
# define ft11 63
#endif
callerSaves :: GlobalReg -> Bool
......@@ -667,7 +735,7 @@ globalRegMaybe :: GlobalReg -> Maybe RealReg
#if defined(MACHREGS_i386) || defined(MACHREGS_x86_64) \
|| defined(MACHREGS_sparc) || defined(MACHREGS_powerpc) \
|| defined(MACHREGS_arm) || defined(MACHREGS_aarch64) \
|| defined(MACHREGS_s390x)
|| defined(MACHREGS_s390x) || defined(MACHREGS_riscv64)
# if defined(REG_Base)
globalRegMaybe BaseReg = Just (RealRegSingle REG_Base)
# endif
......
......@@ -663,6 +663,68 @@ the stack. See Note [Overlapping global registers] for implications.
#define CALLER_SAVES_D5
#define CALLER_SAVES_D6
/* -----------------------------------------------------------------------------
The riscv64 register mapping
Register | Role(s) | Call effect
------------+-----------------------------------------+-------------
zero | Hard-wired zero | -
ra | Return address | caller-saved
sp | Stack pointer | callee-saved
gp | Global pointer | callee-saved
tp | Thread pointer | callee-saved
t0,t1,t2 | - | caller-saved
s0 | Frame pointer | callee-saved
s1 | - | callee-saved
a0,a1 | Arguments / return values | caller-saved
a2..a7 | Arguments | caller-saved
s2..s11 | - | callee-saved
t3..t6 | - | caller-saved
ft0..ft7 | - | caller-saved
fs0,fs1 | - | callee-saved
fa0,fa1 | Arguments / return values | caller-saved
fa2..fa7 | Arguments | caller-saved
fs2..fs11 | - | callee-saved
ft8..ft11 | - | caller-saved
Each general purpose register as well as each floating-point
register is 64 bits wide.
-------------------------------------------------------------------------- */
#elif defined(MACHREGS_riscv64)
#define REG(x) __asm__(#x)
#define REG_Base s1
#define REG_Sp s2
#define REG_Hp s3
#define REG_R1 s4
#define REG_R2 s5
#define REG_R3 s6
#define REG_R4 s7
#define REG_R5 s8
#define REG_R6 s9
#define REG_R7 s10
#define REG_SpLim s11
#define REG_F1 fs0
#define REG_F2 fs1
#define REG_F3 fs2
#define REG_F4 fs3
#define REG_F5 fs4
#define REG_F6 fs5
#define REG_D1 fs6
#define REG_D2 fs7
#define REG_D3 fs8
#define REG_D4 fs9
#define REG_D5 fs10
#define REG_D6 fs11
#define MAX_REAL_FLOAT_REG 6
#define MAX_REAL_DOUBLE_REG 6
#else
#error Cannot find platform to give register info for
......
......@@ -71,6 +71,10 @@
#define MACHREGS_s390x 1
#endif
#if defined(riscv64_HOST_ARCH)
#define MACHREGS_riscv64 1
#endif
#endif
#include "MachRegs.h"
......@@ -343,6 +343,8 @@ write_barrier(void) {
#elif defined(powerpc_HOST_ARCH) || defined(powerpc64_HOST_ARCH) \
|| defined(powerpc64le_HOST_ARCH)
__asm__ __volatile__ ("lwsync" : : : "memory");
#elif defined(riscv64_HOST_ARCH)
__asm__ __volatile__ ("" : : : "memory");
#elif defined(s390x_HOST_ARCH)
__asm__ __volatile__ ("" : : : "memory");
#elif defined(sparc_HOST_ARCH)
......@@ -366,6 +368,8 @@ store_load_barrier(void) {
#elif defined(powerpc_HOST_ARCH) || defined(powerpc64_HOST_ARCH) \
|| defined(powerpc64le_HOST_ARCH)
__asm__ __volatile__ ("sync" : : : "memory");
#elif defined(riscv64_HOST_ARCH)
__asm__ __volatile__ ("fence" : : : "memory");
#elif defined(s390x_HOST_ARCH)
__asm__ __volatile__ ("bcr 14,0" : : : "memory");
#elif defined(sparc_HOST_ARCH)
......@@ -390,6 +394,8 @@ load_load_barrier(void) {
#elif defined(powerpc_HOST_ARCH) || defined(powerpc64_HOST_ARCH) \
|| defined(powerpc64le_HOST_ARCH)
__asm__ __volatile__ ("lwsync" : : : "memory");
#elif defined(riscv64_HOST_ARCH)
__asm__ __volatile__ ("" : : : "memory");
#elif defined(s390x_HOST_ARCH)
__asm__ __volatile__ ("" : : : "memory");
#elif defined(sparc_HOST_ARCH)
......
......@@ -37,6 +37,7 @@ data Arch
| ArchX86_64
| ArchPPC
| ArchPPC_64 PPC_64ABI
| ArchRISCV64
| ArchS390X
| ArchSPARC
| ArchSPARC64
......@@ -124,6 +125,7 @@ stringEncodeArch = \case
ArchPPC -> "powerpc"
ArchPPC_64 ELF_V1 -> "powerpc64"
ArchPPC_64 ELF_V2 -> "powerpc64le"
ArchRISCV64 -> "riscv64"
ArchS390X -> "s390x"
ArchSPARC -> "sparc"
ArchSPARC64 -> "sparc64"
......
......@@ -72,6 +72,7 @@ data Arch = ArchSPARC
| ArchARM64
| ArchPPC64
| ArchPPC64LE
| ArchRISCV64
| ArchS390X
deriving Show
......@@ -107,6 +108,8 @@ mArch =
Just ArchPPC64
#elif defined(powerpc64le_HOST_ARCH)
Just ArchPPC64LE
#elif defined(riscv64_HOST_ARCH)
Just ArchRISCV64
#elif defined(s390x_HOST_ARCH)
Just ArchS390X
#else
......@@ -274,6 +277,26 @@ mkJumpToAddr' platform a = case platform of
0x618C0000 .|. lo16 w32,
0x7D8903A6, 0x4E800420 ]
ArchRISCV64 ->
-- Generates:
-- .L0: auipc t0,%pcrel_hi(.L1)
-- ld t0,%pcrel_lo(.L0)(a0)
-- jr t0
-- .L1:
-- .dword <addr>
--
-- which looks like:
-- 0: 00000297 auipc t0,0x0
-- 4: 00a2b283 ld t0,10(t0) # a <f+0xa>
-- 8: 8282 jr t0
-- with addr at a.
let w64 = fromIntegral (funPtrToInt a) :: Word64
in Left [ 0x97, 0x02, 0x00, 0x00, 0x83, 0xb2, 0xa2, 0x00,
0x82, 0x82,
byte0 w64, byte1 w64, byte2 w64, byte3 w64,
byte4 w64, byte5 w64, byte6 w64, byte7 w64 ]
ArchS390X ->
-- Let 0xAABBCCDDEEFFGGHH be the address to jump to.
-- The following code loads the address into scratch
......
......@@ -37,6 +37,8 @@
,("powerpc64le-unknown-linux-gnu", ("e-m:e-i64:64-n32:64", "ppc64le", ""))
,("powerpc64le-unknown-linux-musl", ("e-m:e-i64:64-n32:64", "ppc64le", "+secure-plt"))
,("powerpc64le-unknown-linux", ("e-m:e-i64:64-n32:64", "ppc64le", ""))
,("riscv64-unknown-linux-gnu", ("e-m:e-p:64:64-i64:64-i128:128-n64-S128", "generic-rv64", "+m +a +f +d +c +relax"))
,("riscv64-unknown-linux", ("e-m:e-p:64:64-i64:64-i128:128-n64-S128", "generic-rv64", "+m +a +f +d +c +relax"))
,("s390x-ibm-linux", ("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64", "z10", ""))
,("i386-apple-darwin", ("e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128", "yonah", ""))
,("x86_64-apple-darwin", ("e-m:o-i64:64-f80:128-n8:16:32:64-S128", "core2", ""))
......
......@@ -179,7 +179,7 @@ ifeq "$(TargetArch_CPP)" "arm"
# We don't support load/store barriers pre-ARMv7. See #10433.
ArchSupportsSMP=$(if $(filter $(ARM_ISA),ARMv5 ARMv6),NO,YES)
else
ArchSupportsSMP=$(strip $(patsubst $(TargetArch_CPP), YES, $(findstring $(TargetArch_CPP), i386 x86_64 sparc powerpc powerpc64 powerpc64le s390x aarch64)))
ArchSupportsSMP=$(strip $(patsubst $(TargetArch_CPP), YES, $(findstring $(TargetArch_CPP), i386 x86_64 sparc powerpc powerpc64 powerpc64le riscv64 s390x aarch64)))
endif
# The THREADED_RTS requires `BaseReg` to be in a register and the
......@@ -359,7 +359,7 @@ LibdwIncludeDir=@LibdwIncludeDir@
# GHC needs arch-specific tweak at least in
# rts/Libdw.c:set_initial_registers()
GhcRtsWithLibdw=$(strip $(if $(filter $(TargetArch_CPP),i386 x86_64 s390x),@UseLibdw@,NO))
GhcRtsWithLibdw=$(strip $(if $(filter $(TargetArch_CPP),i386 x86_64 riscv64 s390x),@UseLibdw@,NO))
################################################################################
#
......
......@@ -330,6 +330,49 @@ static bool set_initial_registers(Dwfl_Thread *thread,
);
return dwfl_thread_state_registers(thread, 0, 9, regs);
}
#elif defined(riscv64_HOST_ARCH)
static bool set_initial_registers(Dwfl_Thread *thread,
void *arg STG_UNUSED) {
Dwarf_Word regs[32];
__asm__ ("sd x1,0x08(%0)\t\n"
"sd x2,0x10(%0)\t\n"
"sd x3,0x18(%0)\t\n"
"sd x4,0x20(%0)\t\n"
"sd x5,0x28(%0)\t\n"
"sd x6,0x30(%0)\t\n"
"sd x7,0x38(%0)\t\n"
"sd x8,0x40(%0)\t\n"
"sd x9,0x48(%0)\t\n"
"sd x10,0x50(%0)\t\n"
"sd x11,0x58(%0)\t\n"
"sd x12,0x60(%0)\t\n"
"sd x13,0x68(%0)\t\n"
"sd x14,0x70(%0)\t\n"
"sd x15,0x78(%0)\t\n"
"sd x16,0x80(%0)\t\n"
"sd x17,0x88(%0)\t\n"
"sd x18,0x90(%0)\t\n"
"sd x19,0x98(%0)\t\n"
"sd x20,0xa0(%0)\t\n"
"sd x21,0xa8(%0)\t\n"
"sd x22,0xb0(%0)\t\n"
"sd x23,0xb8(%0)\t\n"
"sd x24,0xc0(%0)\t\n"
"sd x25,0xc8(%0)\t\n"
"sd x26,0xd0(%0)\t\n"
"sd x27,0xd8(%0)\t\n"
"sd x28,0xe0(%0)\t\n"
"sd x29,0xe8(%0)\t\n"
"sd x30,0xf0(%0)\t\n"
"sd x31,0xf8(%0)\t\n"
"auipc t0,0\t\n"
"sd t0,0(%0)\t\n"
: /* no output */
:"r" (&regs[0]) /* input */
:"t0" /* clobbered */
);
return dwfl_thread_state_registers(thread, 0, 64, regs);
}
#elif defined(s390x_HOST_ARCH)
static bool set_initial_registers(Dwfl_Thread *thread,
void *arg STG_UNUSED) {
......
......@@ -141,6 +141,149 @@ StgReturn:
# endif // aix_HOST_OS
#elif defined(riscv64_HOST_ARCH)
# define STACK_FRAME_SIZE (RESERVED_C_STACK_BYTES+208)
.text
.align 1
.globl StgRun
.type StgRun, @function
StgRun:
.cfi_startproc
addi sp,sp,-208
.cfi_def_cfa_offset 208
/* save callee-saved registers */
sd ra,200(sp)
sd s0,192(sp)
sd s1,184(sp)
sd s2,176(sp)
sd s3,168(sp)
sd s4,160(sp)
sd s5,152(sp)
sd s6,144(sp)
sd s7,136(sp)
sd s8,128(sp)
sd s9,120(sp)
sd s10,112(sp)
sd s11,104(sp)
fsd fs0,88(sp)
fsd fs1,80(sp)
fsd fs2,72(sp)
fsd fs3,64(sp)
fsd fs4,56(sp)
fsd fs5,48(sp)
fsd fs6,40(sp)
fsd fs7,32(sp)
fsd fs8,24(sp)
fsd fs9,16(sp)
fsd fs10,8(sp)
fsd fs11,0(sp)
/* allocate stack frame */
li t0,-(RESERVED_C_STACK_BYTES)
add sp,sp,t0
.cfi_def_cfa_offset STACK_FRAME_SIZE
.cfi_offset 1, -8
.cfi_offset 8, -16
.cfi_offset 9, -24
.cfi_offset 18, -32
.cfi_offset 19, -40
.cfi_offset 20, -48
.cfi_offset 21, -56
.cfi_offset 22, -64
.cfi_offset 23, -72
.cfi_offset 24, -80
.cfi_offset 25, -88
.cfi_offset 26, -96
.cfi_offset 27, -104
.cfi_offset 40, -120
.cfi_offset 41, -128
.cfi_offset 50, -136
.cfi_offset 51, -144
.cfi_offset 52, -152
.cfi_offset 53, -160
.cfi_offset 54, -168
.cfi_offset 55, -176
.cfi_offset 56, -184
.cfi_offset 57, -192
.cfi_offset 58, -200
.cfi_offset 59, -208
/* set STGs BaseReg from RISCV a1 */
mv s1,a1
/* jump to STG function */
jr a0
.cfi_endproc
.size StgRun, .-StgRun
.text
.align 1
.globl StgReturn
.type StgReturn, @function
StgReturn:
.cfi_startproc
/* set return value from STGs R1 (RISCV s4) */
mv a0,s4
/* deallocate stack frame */
li t0,RESERVED_C_STACK_BYTES
add sp,sp,t0
.cfi_def_cfa_offset 208
/* restore callee-saved registers */
ld ra,200(sp)
.cfi_restore 1
ld s0,192(sp)
.cfi_restore 8
ld s1,184(sp)
.cfi_restore 9
ld s2,176(sp)
.cfi_restore 18
ld s3,168(sp)
.cfi_restore 19
ld s4,160(sp)
.cfi_restore 20
ld s5,152(sp)
.cfi_restore 21
ld s6,144(sp)
.cfi_restore 22