Main.hs 21.1 KB
Newer Older
1
{-# OPTIONS -fno-warn-missing-signatures #-}
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65
-----------------------------------------------------------------------------
--
-- The register allocator
--
-- (c) The University of Glasgow 2004
--
-----------------------------------------------------------------------------

{-
The algorithm is roughly:
 
  1) Compute strongly connected components of the basic block list.

  2) Compute liveness (mapping from pseudo register to
     point(s) of death?).

  3) Walk instructions in each basic block.  We keep track of
	(a) Free real registers (a bitmap?)
	(b) Current assignment of temporaries to machine registers and/or
	    spill slots (call this the "assignment").
     	(c) Partial mapping from basic block ids to a virt-to-loc mapping.
	    When we first encounter a branch to a basic block,
	    we fill in its entry in this table with the current mapping.

     For each instruction:
	(a) For each real register clobbered by this instruction:
	    If a temporary resides in it,
		If the temporary is live after this instruction,
		    Move the temporary to another (non-clobbered & free) reg,
		    or spill it to memory.  Mark the temporary as residing
		    in both memory and a register if it was spilled (it might
		    need to be read by this instruction).
	    (ToDo: this is wrong for jump instructions?)

	(b) For each temporary *read* by the instruction:
	    If the temporary does not have a real register allocation:
		- Allocate a real register from the free list.  If
		  the list is empty:
		  - Find a temporary to spill.  Pick one that is
		    not used in this instruction (ToDo: not
		    used for a while...)
		  - generate a spill instruction
		- If the temporary was previously spilled,
		  generate an instruction to read the temp from its spill loc.
	    (optimisation: if we can see that a real register is going to
            be used soon, then don't use it for allocation).

	(c) Update the current assignment

	(d) If the intstruction is a branch:
	      if the destination block already has a register assignment,
	        Generate a new block with fixup code and redirect the
		jump to the new block.
	      else,
		Update the block id->assignment mapping with the current
		assignment.

	(e) Delete all register assignments for temps which are read
	    (only) and die here.  Update the free register list.

	(f) Mark all registers clobbered by this instruction as not free,
	    and mark temporaries which have been spilled due to clobbering
	    as in memory (step (a) marks then as in both mem & reg).

66
	(g) For each temporary *written* by this instruction:
67 68
	    Allocate a real register as for (b), spilling something
	    else if necessary.
69 70 71
		- except when updating the assignment, drop any memory
		  locations that the temporary was previously in, since
		  they will be no longer valid after this instruction.
72 73 74 75 76 77 78 79 80 81 82 83

	(h) Delete all register assignments for temps which are
	    written and die here (there should rarely be any).  Update
	    the free register list.

	(i) Rewrite the instruction with the new mapping.

	(j) For each spilled reg known to be now dead, re-add its stack slot
	    to the free list.

-}

84
module RegAlloc.Linear.Main (
85
  	regAlloc,
86 87
	module	RegAlloc.Linear.Base,
	module	RegAlloc.Linear.Stats
88 89 90 91
  ) where

#include "HsVersions.h"

92 93 94 95 96 97

import RegAlloc.Linear.State
import RegAlloc.Linear.Base
import RegAlloc.Linear.StackMap
import RegAlloc.Linear.FreeRegs
import RegAlloc.Linear.Stats
98
import RegAlloc.Linear.JoinToTargets
99

100
import BlockId
101 102
import Regs
import Instrs
103
import RegAllocInfo
104
import RegLiveness
105
import Cmm hiding (RegSet)
106 107

import Digraph
108
import Unique
109
import UniqSet
110
import UniqFM
111
import UniqSupply
112
import Outputable
113
import FastString
114

115 116 117
import Data.Maybe
import Data.List
import Control.Monad
118

119
#include "../includes/MachRegs.h"
120

121

122 123 124
-- -----------------------------------------------------------------------------
-- Top level of the register allocator

125 126 127
-- Allocate registers
regAlloc 
	:: LiveCmmTop
128
	-> UniqSM (NatCmmTop, Maybe RegAllocStats)
129

Ben.Lippmeier@anu.edu.au's avatar
Ben.Lippmeier@anu.edu.au committed
130
regAlloc (CmmData sec d) 
131 132 133
 	= return
		( CmmData sec d
		, Nothing )
134
	
135
regAlloc (CmmProc (LiveInfo info _ _) lbl params (ListGraph []))
136 137
	= return ( CmmProc info lbl params (ListGraph [])
		 , Nothing )
138
	
139
regAlloc (CmmProc static lbl params (ListGraph comps))
140 141 142 143
	| LiveInfo info (Just first_id) block_live	<- static
	= do	
 		-- do register allocation on each component.
		(final_blocks, stats)
144
			<- linearRegAlloc first_id block_live 
145
			$ map (\b -> case b of 
Ben.Lippmeier@anu.edu.au's avatar
Ben.Lippmeier@anu.edu.au committed
146 147
					BasicBlock _ [b]	-> AcyclicSCC b
					BasicBlock _ bs		-> CyclicSCC  bs)
148 149 150 151 152 153 154
			$ comps

		-- make sure the block that was first in the input list
		--	stays at the front of the output
		let ((first':_), rest')
				= partition ((== first_id) . blockId) final_blocks

155
		return	( CmmProc info lbl params (ListGraph (first' : rest'))
156
			, Just stats)
157
	
Ben.Lippmeier@anu.edu.au's avatar
Ben.Lippmeier@anu.edu.au committed
158 159 160
-- bogus. to make non-exhaustive match warning go away.
regAlloc (CmmProc _ _ _ _)
	= panic "RegAllocLinear.regAlloc: no match"
161

162

163 164 165
-- -----------------------------------------------------------------------------
-- Linear sweep to allocate registers

166 167

-- | Do register allocation on some basic blocks.
168 169
--   But be careful to allocate a block in an SCC only if it has
--   an entry in the block map or it is the first block.
170
--
171
linearRegAlloc
172 173
	:: BlockId                      -- ^ the first block
        -> BlockMap RegSet		-- ^ live regs on entry to each basic block
174 175 176
	-> [SCC LiveBasicBlock]		-- ^ instructions annotated with "deaths"
	-> UniqSM ([NatBasicBlock], RegAllocStats)

177
linearRegAlloc first_id block_live sccs
178
 = do	us	<- getUs
Ben.Lippmeier@anu.edu.au's avatar
Ben.Lippmeier@anu.edu.au committed
179
 	let (_, _, stats, blocks) =
180
		runR emptyBlockMap initFreeRegs emptyRegMap emptyStackMap us
181
			$ linearRA_SCCs first_id block_live [] sccs
182 183 184

	return	(blocks, stats)

185
linearRA_SCCs _ _ blocksAcc []
186 187
	= return $ reverse blocksAcc

188
linearRA_SCCs first_id block_live blocksAcc (AcyclicSCC block : sccs) 
189
 = do	blocks'	<- processBlock block_live block
190
	linearRA_SCCs first_id block_live 
191 192 193
		((reverse blocks') ++ blocksAcc)
		sccs

194 195 196 197 198 199 200 201 202 203 204
linearRA_SCCs first_id block_live blocksAcc (CyclicSCC blocks : sccs) 
 = do	let process [] []         accum = return $ reverse accum
            process [] next_round accum = process next_round [] accum
            process (b@(BasicBlock id _) : blocks) next_round accum =
              do block_assig <- getBlockAssigR
                 if isJust (lookupBlockEnv block_assig id) || id == first_id
                  then do b'  <- processBlock block_live b
                          process blocks next_round (b' : accum)
                  else process blocks (b : next_round) accum
        blockss' <- process blocks [] (return [])
	linearRA_SCCs first_id block_live
205 206 207 208 209 210 211 212 213 214 215 216 217 218
		(reverse (concat blockss') ++ blocksAcc)
		sccs
		

-- | Do register allocation on this basic block
--
processBlock
	:: BlockMap RegSet 		-- ^ live regs on entry to each basic block
	-> LiveBasicBlock 		-- ^ block to do register allocation on
	-> RegM [NatBasicBlock]		-- ^ block with registers allocated

processBlock block_live (BasicBlock id instrs)
 = do 	initBlock id
 	(instrs', fixups)
219
		<- linearRA block_live [] [] id instrs
220 221 222 223 224 225 226 227 228

	return	$ BasicBlock id instrs' : fixups


-- | Load the freeregs and current reg assignment into the RegM state
--	for the basic block with this BlockId.
initBlock :: BlockId -> RegM ()
initBlock id
 = do	block_assig	<- getBlockAssigR
229
  	case lookupBlockEnv block_assig id of
230 231 232 233 234 235 236 237 238 239 240 241
	        -- no prior info about this block: assume everything is
	        -- free and the assignment is empty.
	 	Nothing
		 -> do	setFreeRegsR	initFreeRegs
		 	setAssigR	emptyRegMap

		-- load info about register assignments leading into this block.
		Just (freeregs, assig)
		 -> do	setFreeRegsR 	freeregs
			setAssigR	assig


242
-- | Do allocation for a sequence of instructions.
243
linearRA
244 245 246 247 248
	:: BlockMap RegSet		-- ^ map of what vregs are live on entry to each block.
	-> [Instr] 			-- ^ accumulator for instructions already processed.
	-> [NatBasicBlock] 		-- ^ accumulator for blocks of fixup code.
	-> BlockId			-- ^ id of the current block, for debugging.
	-> [LiveInstr]			-- ^ liveness annotated instructions in this block.
249

250 251
	-> RegM ( [Instr]		--   instructions after register allocation
		, [NatBasicBlock])	--   fresh blocks of fixup code.
252

253

254 255 256 257 258 259 260 261 262 263 264 265
linearRA _          accInstr accFixup _ []
	= return 
		( reverse accInstr	-- instrs need to be returned in the correct order.
		, accFixup)		-- it doesn't matter what order the fixup blocks are returned in.


linearRA block_live accInstr accFixups id (instr:instrs)
 = do
 	(accInstr', new_fixups) 
		<- raInsn block_live accInstr id instr

	linearRA block_live accInstr' (new_fixups ++ accFixups) id instrs
266 267


268 269 270 271 272 273 274 275 276 277 278
-- | Do allocation for a single instruction.
raInsn  
	:: BlockMap RegSet		-- ^ map of what vregs are love on entry to each block.
	-> [Instr]			-- ^ accumulator for instructions already processed.
	-> BlockId			-- ^ the id of the current block, for debugging
	-> LiveInstr 			-- ^ the instr to have its regs allocated, with liveness info.
	-> RegM 
		( [Instr]		-- new instructions
		, [NatBasicBlock])	-- extra fixup blocks

raInsn _     new_instrs _ (Instr (COMMENT _) Nothing)
279 280
 = return (new_instrs, [])

281
raInsn _     new_instrs _ (Instr (DELTA n) Nothing)  
282
 = do
283 284 285
    setDeltaR n
    return (new_instrs, [])

286
raInsn block_live new_instrs id (Instr instr (Just live))
287
 = do
288 289 290 291
    assig    <- getAssigR

    -- If we have a reg->reg move between virtual registers, where the
    -- src register is not live after this instruction, and the dst
292 293 294 295 296
    -- register does not already have an assignment,
    -- and the source register is assigned to a register, not to a spill slot,
    -- then we can eliminate the instruction.
    -- (we can't eliminitate it if the source register is on the stack, because
    --  we do not want to use one spill slot for different virtual registers)
297
    case isRegRegMove instr of
298
	Just (src,dst)	| src `elementOfUniqSet` (liveDieRead live), 
299
		  	  isVirtualReg dst,
300 301
		 	  not (dst `elemUFM` assig),
		 	  Just (InReg _) <- (lookupUFM assig src) -> do
302 303 304 305 306 307 308 309 310 311
	   case src of
	      RealReg i -> setAssigR (addToUFM assig dst (InReg i))
		-- if src is a fixed reg, then we just map dest to this
		-- reg in the assignment.  src must be an allocatable reg,
		-- otherwise it wouldn't be in r_dying.
	      _virt -> case lookupUFM assig src of
		         Nothing -> panic "raInsn"
			 Just loc ->
			   setAssigR (addToUFM (delFromUFM assig src) dst loc)

312
	   -- we have eliminated this instruction
313
          {-
314 315
	  freeregs <- getFreeRegsR
    	  assig <- getAssigR
316 317
          pprTrace "raInsn" (text "ELIMINATED: " <> docToSDoc (pprInstr instr) 
	  		$$ ppr r_dying <+> ppr w_dying $$ text (show freeregs) $$ ppr assig) $ do
318
          -}
319
	   return (new_instrs, [])
320

321
	_ -> genRaInsn block_live new_instrs id instr 
322 323 324 325
			(uniqSetToList $ liveDieRead live) 
			(uniqSetToList $ liveDieWrite live)


326 327 328 329
raInsn _ _ id instr
	= pprPanic "raInsn" (text "no match for:" <> ppr instr)


330 331


332
genRaInsn block_live new_instrs block_id instr r_dying w_dying =
333 334 335
    case regUsage instr              of { RU read written ->
    case partition isRealReg written of { (real_written1,virt_written) ->
    do
336 337 338 339 340 341 342 343 344 345
    let 
	real_written = [ r | RealReg r <- real_written1 ]

	-- we don't need to do anything with real registers that are
	-- only read by this instr.  (the list is typically ~2 elements,
	-- so using nub isn't a problem).
	virt_read = nub (filter isVirtualReg read)
    -- in

    -- (a) save any temporaries which will be clobbered by this instruction
346
    clobber_saves <- saveClobberedTemps real_written r_dying
347

348 349

{-  freeregs <- getFreeRegsR
350
    assig <- getAssigR
351 352 353 354 355
    pprTrace "raInsn" 
    	(docToSDoc (pprInstr instr) $$ ppr r_dying <+> ppr w_dying $$ ppr virt_read <+> ppr virt_written 
		$$ text (show freeregs) $$ ppr assig) 
		$ do
-}
356 357 358 359 360 361 362 363 364 365

    -- (b), (c) allocate real regs for all regs read by this instruction.
    (r_spills, r_allocd) <- 
	allocateRegsAndSpill True{-reading-} virt_read [] [] virt_read

    -- (d) Update block map for new destinations
    -- NB. do this before removing dead regs from the assignment, because
    -- these dead regs might in fact be live in the jump targets (they're
    -- only dead in the code that follows in the current basic block).
    (fixup_blocks, adjusted_instr)
366
	<- joinToTargets block_live block_id instr
367 368 369 370 371 372

    -- (e) Delete all register assignments for temps which are read
    --     (only) and die here.  Update the free register list.
    releaseRegs r_dying

    -- (f) Mark regs which are clobbered as unallocatable
373
    clobberRegs real_written
374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399

    -- (g) Allocate registers for temporaries *written* (only)
    (w_spills, w_allocd) <- 
	allocateRegsAndSpill False{-writing-} virt_written [] [] virt_written

    -- (h) Release registers for temps which are written here and not
    -- used again.
    releaseRegs w_dying

    let
	-- (i) Patch the instruction
	patch_map = listToUFM   [ (t,RealReg r) | 
				  (t,r) <- zip virt_read r_allocd
					  ++ zip virt_written w_allocd ]

	patched_instr = patchRegs adjusted_instr patchLookup
	patchLookup x = case lookupUFM patch_map x of
				Nothing -> x
				Just y  -> y
    -- in

    -- pprTrace "patched" (docToSDoc (pprInstr patched_instr)) $ do

    -- (j) free up stack slots for dead spilled regs
    -- TODO (can't be bothered right now)

400 401 402 403 404 405 406 407 408
    -- erase reg->reg moves where the source and destination are the same.
    --	If the src temp didn't die in this instr but happened to be allocated
    --	to the same real reg as the destination, then we can erase the move anyway.
	squashed_instr	= case isRegRegMove patched_instr of
				Just (src, dst)
				 | src == dst	-> []
				_		-> [patched_instr]

    return (squashed_instr ++ w_spills ++ reverse r_spills
409 410
		 ++ clobber_saves ++ new_instrs,
	    fixup_blocks)
411
  }}
412 413 414 415 416 417 418 419 420

-- -----------------------------------------------------------------------------
-- releaseRegs

releaseRegs regs = do
  assig <- getAssigR
  free <- getFreeRegsR
  loop assig free regs 
 where
Ben.Lippmeier@anu.edu.au's avatar
Ben.Lippmeier@anu.edu.au committed
421
  loop _     free _ | free `seq` False = undefined
422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448
  loop assig free [] = do setAssigR assig; setFreeRegsR free; return ()
  loop assig free (RealReg r : rs) = loop assig (releaseReg r free) rs
  loop assig free (r:rs) = 
     case lookupUFM assig r of
	Just (InBoth real _) -> loop (delFromUFM assig r) (releaseReg real free) rs
	Just (InReg real) -> loop (delFromUFM assig r) (releaseReg real free) rs
	_other            -> loop (delFromUFM assig r) free rs

-- -----------------------------------------------------------------------------
-- Clobber real registers

{-
For each temp in a register that is going to be clobbered:
  - if the temp dies after this instruction, do nothing
  - otherwise, put it somewhere safe (another reg if possible,
    otherwise spill and record InBoth in the assignment).

for allocateRegs on the temps *read*,
  - clobbered regs are allocatable.

for allocateRegs on the temps *written*, 
  - clobbered regs are not allocatable.
-}

saveClobberedTemps
   :: [RegNo]		   -- real registers clobbered by this instruction
   -> [Reg]		   -- registers which are no longer live after this insn
449 450
   -> RegM [Instr] 	   -- return: instructions to spill any temps that will
		 	   -- be clobbered.
451

452
saveClobberedTemps [] _ = return [] -- common case
453 454 455 456 457 458 459
saveClobberedTemps clobbered dying =  do
  assig <- getAssigR
  let
	to_spill  = [ (temp,reg) | (temp, InReg reg) <- ufmToList assig,
				   reg `elem` clobbered,
				   temp `notElem` map getUnique dying  ]
  -- in
460
  (instrs,assig') <- clobber assig [] to_spill
461
  setAssigR assig'
462
  return instrs
463
 where
464 465
  clobber assig instrs [] = return (instrs,assig)
  clobber assig instrs ((temp,reg):rest)
466 467
    = do
	--ToDo: copy it to another register if possible
468 469 470 471
	(spill,slot) <- spillR (RealReg reg) temp
	recordSpill (SpillClobber temp)

	let new_assign	= addToUFM assig temp (InBoth reg slot)
472
	clobber new_assign (spill : COMMENT (fsLit "spill clobber") : instrs) rest
473

474 475 476
clobberRegs :: [RegNo] -> RegM ()
clobberRegs [] = return () -- common case
clobberRegs clobbered = do
477
  freeregs <- getFreeRegsR
478
--  setFreeRegsR $! foldr grabReg freeregs clobbered
479
  setFreeRegsR $! foldr allocateReg freeregs clobbered
480

481
  assig <- getAssigR
482 483 484 485 486 487 488 489 490 491 492
  setAssigR $! clobber assig (ufmToList assig)
 where
    -- if the temp was InReg and clobbered, then we will have
    -- saved it in saveClobberedTemps above.  So the only case
    -- we have to worry about here is InBoth.  Note that this
    -- also catches temps which were loaded up during allocation
    -- of read registers, not just those saved in saveClobberedTemps.
  clobber assig [] = assig
  clobber assig ((temp, InBoth reg slot) : rest)
	| reg `elem` clobbered
	= clobber (addToUFM assig temp (InMem slot)) rest
Ben.Lippmeier@anu.edu.au's avatar
Ben.Lippmeier@anu.edu.au committed
493
  clobber assig (_:rest)
494
	= clobber assig rest 
495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513

-- -----------------------------------------------------------------------------
-- allocateRegsAndSpill

-- This function does several things:
--   For each temporary referred to by this instruction,
--   we allocate a real register (spilling another temporary if necessary).
--   We load the temporary up from memory if necessary.
--   We also update the register assignment in the process, and
--   the list of free registers and free stack slots.

allocateRegsAndSpill
	:: Bool			-- True <=> reading (load up spilled regs)
	-> [Reg]		-- don't push these out
	-> [Instr]		-- spill insns
	-> [RegNo]		-- real registers allocated (accum.)
	-> [Reg]		-- temps to allocate
	-> RegM ([Instr], [RegNo])

Ben.Lippmeier@anu.edu.au's avatar
Ben.Lippmeier@anu.edu.au committed
514
allocateRegsAndSpill _       _    spills alloc []
515 516 517 518 519 520 521 522 523 524
  = return (spills,reverse alloc)

allocateRegsAndSpill reading keep spills alloc (r:rs) = do
  assig <- getAssigR
  case lookupUFM assig r of
  -- case (1a): already in a register
     Just (InReg my_reg) ->
	allocateRegsAndSpill reading keep spills (my_reg:alloc) rs

  -- case (1b): already in a register (and memory)
525
  -- NB1. if we're writing this register, update its assignemnt to be
526
  -- InReg, because the memory value is no longer valid.
527 528
  -- NB2. This is why we must process written registers here, even if they
  -- are also read by the same instruction.
Ben.Lippmeier@anu.edu.au's avatar
Ben.Lippmeier@anu.edu.au committed
529
     Just (InBoth my_reg _) -> do
530
	when (not reading) (setAssigR (addToUFM assig r (InReg my_reg)))
531 532 533 534 535 536 537 538 539
   	allocateRegsAndSpill reading keep spills (my_reg:alloc) rs

  -- Not already in a register, so we need to find a free one...
     loc -> do
	freeregs <- getFreeRegsR

        case getFreeRegs (regClass r) freeregs of

      	-- case (2): we have a free register
540
      	  my_reg:_ -> {- pprTrace "alloc" (ppr r <+> ppr my_reg <+> ppr freeClass) $ -}
541
	    do
542
    	    spills'   <- loadTemp reading r loc my_reg spills
543 544 545
	    let new_loc 
		 | Just (InMem slot) <- loc, reading = InBoth my_reg slot
		 | otherwise		             = InReg my_reg
546
	    setAssigR (addToUFM assig r $! new_loc)
547
	    setFreeRegsR $ allocateReg my_reg freeregs
548 549 550 551 552 553 554 555 556 557 558 559 560
    	    allocateRegsAndSpill reading keep spills' (my_reg:alloc) rs

        -- case (3): we need to push something out to free up a register
          [] -> do
	    let
	      keep' = map getUnique keep
	      candidates1 = [ (temp,reg,mem)
			    | (temp, InBoth reg mem) <- ufmToList assig,
			      temp `notElem` keep', regClass (RealReg reg) == regClass r ]
	      candidates2 = [ (temp,reg)
			    | (temp, InReg reg) <- ufmToList assig,
			      temp `notElem` keep', regClass (RealReg reg) == regClass r  ]
	    -- in
561 562
	    ASSERT2(not (null candidates1 && null candidates2), 
		    text (show freeregs) <+> ppr r <+> ppr assig) do
563 564 565 566 567 568 569

	    case candidates1 of

	     -- we have a temporary that is in both register and mem,
	     -- just free up its register for use.
	     -- 
	     (temp,my_reg,slot):_ -> do
570
    	        spills' <- loadTemp reading r loc my_reg spills
571 572 573 574 575 576 577 578 579
    	        let	
	          assig1  = addToUFM assig temp (InMem slot)
	          assig2  = addToUFM assig1 r (InReg my_reg)
 	        -- in
		setAssigR assig2
		allocateRegsAndSpill reading keep spills' (my_reg:alloc) rs

	     -- otherwise, we need to spill a temporary that currently
	     -- resides in a register.
580 581


582
	     [] -> do
583 584 585 586 587

		-- TODO: plenty of room for optimisation in choosing which temp
	        -- to spill.  We just pick the first one that isn't used in 
	        -- the current instruction for now.

588 589
	        let (temp_to_push_out, my_reg) 
			= case candidates2 of
590 591
				[]	-> panic $ "RegAllocLinear.allocRegsAndSpill: no spill candidates"
					++ "assignment: " ++ show (ufmToList assig) ++ "\n"
592 593
				(x:_)	-> x
				
594 595
    	        (spill_insn, slot) <- spillR (RealReg my_reg) temp_to_push_out
		let spill_store	 = (if reading then id else reverse)
596
					[ COMMENT (fsLit "spill alloc") 
597 598 599 600 601 602 603 604
					, spill_insn ]

		-- record that this temp was spilled
		recordSpill (SpillAlloc temp_to_push_out)

		-- update the register assignment
    	        let assig1  = addToUFM assig temp_to_push_out	(InMem slot)
	        let assig2  = addToUFM assig1 r			(InReg my_reg)
605
	        setAssigR assig2
606 607 608 609 610 611

		-- if need be, load up a spilled temp into the reg we've just freed up.
    	        spills' <- loadTemp reading r loc my_reg spills

 	        allocateRegsAndSpill reading keep
			(spill_store ++ spills')
612
		 	(my_reg:alloc) rs
613 614 615 616 617 618 619 620 621 622 623 624 625 626 627


-- | Load up a spilled temporary if we need to.
loadTemp
	:: Bool
	-> Reg 		-- the temp being loaded
	-> Maybe Loc	-- the current location of this temp
	-> RegNo	-- the hreg to load the temp into
	-> [Instr]
	-> RegM [Instr]

loadTemp True vreg (Just (InMem slot)) hreg spills
 = do
 	insn <- loadR (RealReg hreg) slot
	recordSpill (SpillLoad $ getUnique vreg)
628
	return	$  COMMENT (fsLit "spill load") : insn : spills
629 630 631 632

loadTemp _ _ _ _ spills =
   return spills