Commit 0b447a84 authored by sewardj's avatar sewardj
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[project @ 2001-12-12 18:12:45 by sewardj]

Make the sparc native code generator work again after recent
primop hackery.

* Track the change from PrimOp to MachOp at the Stix level.

* Teach the sparc insn selector how to generate 64-bit code.

* Fix various bogons in sparc {Int,Double,Float} <-> {Int,Double,Float}
  conversions which only happened to generate correct code by
  accident, so far.

* Synthesise BaseReg from &MainCapability.r on archs which do not
  have BaseReg in a regiser (eg sparc :)

At the moment {add,sub,mul}Int# are not implemented.  To be fixed.
parent 7738ad97
%
% (c) The GRASP/AQUA Project, Glasgow University, 1992-1998
%
% $Id: CLabel.lhs,v 1.49 2001/12/05 17:35:12 sewardj Exp $
% $Id: CLabel.lhs,v 1.50 2001/12/12 18:12:45 sewardj Exp $
%
\section[CLabel]{@CLabel@: Information to make C Labels}
......@@ -44,7 +44,7 @@ module CLabel (
mkIndInfoLabel,
mkIndStaticInfoLabel,
mkRtsGCEntryLabel,
mkMainRegTableLabel,
mkMainCapabilityLabel,
mkCharlikeClosureLabel,
mkIntlikeClosureLabel,
mkMAP_FROZEN_infoLabel,
......@@ -178,7 +178,7 @@ data RtsLabelInfo
| RtsUpdInfo -- upd_frame_info
| RtsSeqInfo -- seq_frame_info
| RtsGCEntryLabel String -- a heap check fail handler, eg stg_chk_2
| RtsMainRegTable -- MainRegTable (??? Capabilities wurble ???)
| RtsMainCapability -- MainCapability
| Rts_Closure String -- misc rts closures, eg CHARLIKE_closure
| Rts_Info String -- misc rts itbls, eg MUT_ARR_PTRS_FROZEN_info
| Rts_Code String -- misc rts code
......@@ -247,7 +247,7 @@ mkSeqInfoLabel = RtsLabel RtsSeqInfo
mkIndInfoLabel = RtsLabel (Rts_Info "stg_IND_info")
mkIndStaticInfoLabel = RtsLabel (Rts_Info "stg_IND_STATIC_info")
mkRtsGCEntryLabel str = RtsLabel (RtsGCEntryLabel str)
mkMainRegTableLabel = RtsLabel RtsMainRegTable
mkMainCapabilityLabel = RtsLabel RtsMainCapability
mkCharlikeClosureLabel = RtsLabel (Rts_Closure "stg_CHARLIKE_closure")
mkIntlikeClosureLabel = RtsLabel (Rts_Closure "stg_INTLIKE_closure")
mkMAP_FROZEN_infoLabel = RtsLabel (Rts_Info "stg_MUT_ARR_PTRS_FROZEN_info")
......@@ -464,7 +464,7 @@ pprCLbl (RtsLabel RtsShouldNeverHappenCode) = ptext SLIT("NULL")
pprCLbl (RtsLabel RtsUpdInfo) = ptext SLIT("stg_upd_frame_info")
pprCLbl (RtsLabel RtsSeqInfo) = ptext SLIT("stg_seq_frame_info")
pprCLbl (RtsLabel RtsMainRegTable) = ptext SLIT("MainRegTable")
pprCLbl (RtsLabel RtsMainCapability) = ptext SLIT("MainCapability")
pprCLbl (RtsLabel (RtsGCEntryLabel str)) = text str
pprCLbl (RtsLabel (Rts_Closure str)) = text str
pprCLbl (RtsLabel (Rts_Info str)) = text str
......
......@@ -127,7 +127,8 @@ absCtoNat absC
_scc_ "x86fp_kludge" x86fp_kludge almost_final `bind` \ final_mach_code ->
_scc_ "vcat" Pretty.vcat (map pprInstr final_mach_code) `bind` \ final_sdoc ->
_scc_ "pprStixTrees" pprStixStmts stixOpt `bind` \ stix_sdoc ->
returnUs (stix_sdoc, final_sdoc)
returnUs ({-\_ -> Pretty.vcat (map pprInstr almost_final),-}
stix_sdoc, final_sdoc)
where
bind f x = x f
......
This diff is collapsed.
......@@ -47,7 +47,7 @@ module MachRegs (
#if sparc_TARGET_ARCH
, fits13Bits
, fpRel, gReg, iReg, lReg, oReg, largeOffsetError
, fp, sp, g0, g1, g2, o0, f0, f6, f8, f26, f27
, fp, sp, g0, g1, g2, o0, o1, f0, f6, f8, f26, f27
#endif
) where
......@@ -55,7 +55,7 @@ module MachRegs (
#include "HsVersions.h"
import AbsCSyn ( MagicId(..) )
import CLabel ( CLabel, mkMainRegTableLabel )
import CLabel ( CLabel, mkMainCapabilityLabel )
import MachOp ( MachOp(..) )
import PrimRep ( PrimRep(..), isFloatingRep )
import Stix ( StixExpr(..), StixReg(..),
......@@ -187,16 +187,26 @@ get_MagicId_reg_or_addr mid
Nothing -> Right (get_MagicId_addr mid)
get_MagicId_addr BaseReg
= panic "MachRegs.get_MagicId_addr of BaseReg"
= -- This arch doesn't have BaseReg in a register, so we have to
-- use &MainRegTable.r instead.
StIndex PtrRep (StCLbl mkMainCapabilityLabel)
(StInt (toInteger OFFW_Capability_r))
get_MagicId_addr mid
= get_Regtable_addr_from_offset (baseRegOffset mid)
get_Regtable_addr_from_offset offset_in_words
= case magicIdRegMaybe BaseReg of
Nothing -> panic "MachRegs.get_Regtable_addr_from_offset: BaseReg not in a reg"
Just rr -> StMachOp MO_Nat_Add
[StReg (StixMagicId BaseReg),
StInt (toInteger (offset_in_words*BYTES_PER_WORD))]
= let ptr_to_RegTable
= case magicIdRegMaybe BaseReg of
Nothing
-> -- This arch doesn't have BaseReg in a register, so we have to
-- use &MainRegTable.r instead.
StIndex PtrRep (StCLbl mkMainCapabilityLabel)
(StInt (toInteger OFFW_Capability_r))
Just _
-> -- It's in a reg, so leave it as it is
StReg (StixMagicId BaseReg)
in
StIndex PtrRep ptr_to_RegTable (StInt (toInteger offset_in_words))
\end{code}
% - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
......@@ -468,7 +478,7 @@ showReg n
| n >= 32 && n < 64 = "%f" ++ show (n-32)
| otherwise = "%unknown_sparc_real_reg_" ++ show n
g0, g1, g2, fp, sp, o0, f0, f1, f6, f8, f22, f26, f27 :: Reg
g0, g1, g2, fp, sp, o0, o1, f0, f1, f6, f8, f22, f26, f27 :: Reg
f6 = RealReg (fReg 6)
f8 = RealReg (fReg 8)
......@@ -486,6 +496,7 @@ g2 = RealReg (gReg 2)
fp = RealReg (iReg 6)
sp = RealReg (oReg 6)
o0 = RealReg (oReg 0)
o1 = RealReg (oReg 1)
f0 = RealReg (fReg 0)
f1 = RealReg (fReg 1)
......
......@@ -1486,7 +1486,10 @@ pprInstr (ANDN b reg1 ri reg2) = pprRegRIReg SLIT("andn") b reg1 ri reg2
pprInstr (OR b reg1 ri reg2)
| not b && reg1 == g0
= hcat [ ptext SLIT("\tmov\t"), pprRI ri, comma, pprReg reg2 ]
= let doit = hcat [ ptext SLIT("\tmov\t"), pprRI ri, comma, pprReg reg2 ]
in case ri of
RIReg rrr | rrr == reg2 -> empty
other -> doit
| otherwise
= pprRegRIReg SLIT("or") b reg1 ri reg2
......
/* --------------------------------------------------------------------------
* $Id: mkNativeHdr.c,v 1.6 2001/11/08 12:46:31 simonmar Exp $
* $Id: mkNativeHdr.c,v 1.7 2001/12/12 18:12:46 sewardj Exp $
*
* (c) The GHC Team, 1992-1998
*
......@@ -44,6 +44,8 @@
#define OFFSET_stgGCEnter1 FUN_OFFSET(stgGCEnter1)
#define OFFSET_stgUpdatePAP FUN_OFFSET(stgUpdatePAP)
#define OFFW_Capability_r OFFSET(cap, cap.r)
#define TSO_SP OFFSET(tso, tso.sp)
#define TSO_SU OFFSET(tso, tso.su)
#define TSO_STACK OFFSET(tso, tso.stack)
......@@ -98,6 +100,10 @@ main()
printf("#define OFFSET_stgGCEnter1 (%d)\n", OFFSET_stgGCEnter1);
printf("#define OFFSET_stgUpdatePAP (%d)\n", OFFSET_stgUpdatePAP);
printf("\n-- Offset of the .r (StgRegTable) field in a Capability\n");
printf("#define OFFW_Capability_r (%d)\n", OFFW_Capability_r);
printf("\n-- Storage Manager offsets for the Native Code Generator\n");
printf("\n-- TSO offsets for the Native Code Generator\n");
......
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