Commit c90d45f2 authored by Simon Marlow's avatar Simon Marlow

fix warnings

parent 096396d9
......@@ -27,10 +27,7 @@ module RegAlloc.Linear.StackMap (
where
import RegAlloc.Linear.FreeRegs
import DynFlags
import Outputable
import UniqFM
import Unique
......@@ -49,7 +46,7 @@ data StackMap
-- | An empty stack map, with all slots available.
emptyStackMap :: DynFlags -> StackMap
emptyStackMap dflags = StackMap 0 emptyUFM
emptyStackMap _ = StackMap 0 emptyUFM
-- | If this vreg unique already has a stack assignment then return the slot number,
......
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