1. 24 Feb, 2012 1 commit
  2. 13 Dec, 2011 1 commit
  3. 23 Oct, 2011 4 commits
  4. 31 Aug, 2011 1 commit
  5. 30 Aug, 2011 1 commit
  6. 16 Aug, 2011 1 commit
  7. 15 Jul, 2011 1 commit
  8. 05 Jul, 2011 1 commit
    • batterseapower's avatar
      Refactoring: use a structured CmmStatics type rather than [CmmStatic] · 54843b5b
      batterseapower authored
      I observed that the [CmmStatics] within CmmData uses the list in a very stylised way.
      The first item in the list is almost invariably a CmmDataLabel. Many parts of the
      compiler pattern match on this list and fail if this is not true.
      
      This patch makes the invariant explicit by introducing a structured type CmmStatics
      that holds the label and the list of remaining [CmmStatic].
      
      There is one wrinkle: the x86 backend sometimes wants to output an alignment directive just
      before the label. However, this can be easily fixed up by parameterising the native codegen
      over the type of CmmStatics (though the GenCmmTop parameterisation) and using a pair
      (Alignment, CmmStatics) there instead.
      
      As a result, I think we will be able to remove CmmAlign and CmmDataLabel from the CmmStatic
      data type, thus nuking a lot of code and failing pattern matches. This change will come as part
      of my next patch.
      54843b5b
  9. 29 May, 2011 1 commit
    • Ian Lynagh's avatar
      Remove most of the CPP from AsmCodeGen · 622c3cfe
      Ian Lynagh authored
      In particular, the "#error" for platforms without a NCG is gone,
      which means the module should now build on all platforms again.
      
      I'm not sure if this is the nicest way to handle multiple platforms
      here, but it works for now.
      622c3cfe
  10. 04 May, 2011 1 commit
    • Simon Marlow's avatar
      The fix for #4914 was wrong and broke other things (see #5149). We · 296388e8
      Simon Marlow authored
      can't emit the ffrees before a conditional jump, because we don't want
      to ffree the stack registers if the jump isn't taken (d'oh).
      
      This commit fixes it properly, by moving the pass that inserts the
      ffrees to *before* we do the jump-shortcutting which introduces the
      conditional non-local jumps.
      296388e8
  11. 27 Apr, 2011 1 commit
    • Edward Z. Yang's avatar
      Implement jump table fix-ups for linear register allocator. · 16a037a8
      Edward Z. Yang authored
      
      
      We achieve this by splitting up instruction selection for case
      switches into two parts: the actual code generation, and the
      generation of the accompanying jump table.  With this scheme,
      the jump fixup code can modify the contents of the jump table
      stored within the JMP_TBL (or BCTL) instruction, before the
      actual data section is created.
      
      SPARC and PPC patches are untested; they might not work!
      Signed-off-by: Edward Z. Yang's avatarEdward Z. Yang <ezyang@mit.edu>
      16a037a8
  12. 30 Mar, 2011 1 commit
  13. 25 Mar, 2011 1 commit
    • Simon Marlow's avatar
      Fix #4914 (I hope) · 9c583846
      Simon Marlow authored
      Here's a bit of erroneous code:
      
      00000c5c <s1ad_info>:
           c5c:       8b 45 08                mov    0x8(%ebp),%eax
           c5f:       d9 46 03                flds   0x3(%esi)
           c62:       dd d9                   fstp   %st(1)
           c64:       d9 55 08                fsts   0x8(%ebp)
           c67:       89 c6                   mov    %eax,%esi
           c69:       c7 45 00 24 0c 00 00    movl   $0xc24,0x0(%ebp)
           c70:       f7 c6 03 00 00 00       test   $0x3,%esi
           c76:       75 ac                   jne    c24 <s1ac_info>
      
      So we should be doing some ffrees before the jne.  The code that
      inserts the ffrees wasn't expecting to do it for a conditional jump,
      because they are usually local, but we have a late optimisation that
      shortcuts jumps-to-jumps, and that can result in a non-local
      conditional jump.
      
      This at least fixes an instance of the bug that I was able to
      reproduce, let's hope there aren't any more.
      9c583846
  14. 24 Jan, 2011 1 commit
    • Simon Marlow's avatar
      Merge in new code generator branch. · 889c084e
      Simon Marlow authored
      This changes the new code generator to make use of the Hoopl package
      for dataflow analysis.  Hoopl is a new boot package, and is maintained
      in a separate upstream git repository (as usual, GHC has its own
      lagging darcs mirror in http://darcs.haskell.org/packages/hoopl).
      
      During this merge I squashed recent history into one patch.  I tried
      to rebase, but the history had some internal conflicts of its own
      which made rebase extremely confusing, so I gave up. The history I
      squashed was:
      
        - Update new codegen to work with latest Hoopl
        - Add some notes on new code gen to cmm-notes
        - Enable Hoopl lag package.
        - Add SPJ note to cmm-notes
        - Improve GC calls on new code generator.
      
      Work in this branch was done by:
         - Milan Straka <fox@ucw.cz>
         - John Dias <dias@cs.tufts.edu>
         - David Terei <davidterei@gmail.com>
      
      Edward Z. Yang <ezyang@mit.edu> merged in further changes from GHC HEAD
      and fixed a few bugs.
      889c084e
  15. 07 Jan, 2011 1 commit
  16. 13 Sep, 2010 1 commit
  17. 04 Feb, 2010 1 commit
    • Simon Marlow's avatar
      Implement SSE2 floating-point support in the x86 native code generator (#594) · 335b9f36
      Simon Marlow authored
      The new flag -msse2 enables code generation for SSE2 on x86.  It
      results in substantially faster floating-point performance; the main
      reason for doing this was that our x87 code generation is appallingly
      bad, and since we plan to drop -fvia-C soon, we need a way to generate
      half-decent floating-point code.
      
      The catch is that SSE2 is only available on CPUs that support it (P4+,
      AMD K8+).  We'll have to think hard about whether we should enable it
      by default for the libraries we ship.  In the meantime, at least
      -msse2 should be an acceptable replacement for "-fvia-C
      -optc-ffast-math -fexcess-precision".
      
      SSE2 also has the advantage of performing all operations at the
      correct precision, so floating-point results are consistent with other
      platforms.
      
      I also tweaked the x87 code generation a bit while I was here, now
      it's slighlty less bad than before.
      335b9f36
  18. 05 Nov, 2009 1 commit
    • dias@cs.tufts.edu's avatar
      Loop problems in native back ends, update to T3286 fix · c55eee3a
      dias@cs.tufts.edu authored
      The native back ends had difficulties with loops;
      in particular the code for branch-chain elimination
      could run in infinite loops or drop basic blocks.
      The old codeGen didn't expose these problems.
      
      Also, my fix for T3286 in the new codegen was getting
      applied to too many (some wrong) cases; a better pattern
      match fixed that.
      c55eee3a
  19. 07 Jul, 2009 1 commit
  20. 19 May, 2009 1 commit
  21. 18 May, 2009 1 commit
    • Ben.Lippmeier@anu.edu.au's avatar
      Split Reg into vreg/hreg and add register pairs · f9288086
      Ben.Lippmeier@anu.edu.au authored
       * The old Reg type is now split into VirtualReg and RealReg.
       * For the graph coloring allocator, the type of the register graph
         is now (Graph VirtualReg RegClass RealReg), which shows that it colors
         in nodes representing virtual regs with colors representing real regs.
         (as was intended)  
       * RealReg contains two contructors, RealRegSingle and RealRegPair,
         where RealRegPair is used to represent a SPARC double reg 
         constructed from two single precision FP regs. 
       * On SPARC we can now allocate double regs into an arbitrary register
         pair, instead of reserving some reg ranges to only hold float/double values. 
      f9288086
  22. 15 Feb, 2009 2 commits
    • Ben.Lippmeier@anu.edu.au's avatar
      20c0e6cc
    • Ben.Lippmeier@anu.edu.au's avatar
      NCG: Split up the native code generator into arch specific modules · b04a210e
      Ben.Lippmeier@anu.edu.au authored
        - nativeGen/Instruction defines a type class for a generic
          instruction set. Each of the instruction sets we have, 
          X86, PPC and SPARC are instances of it.
        
        - The register alloctors use this type class when they need
          info about a certain register or instruction, such as
          regUsage, mkSpillInstr, mkJumpInstr, patchRegs..
        
        - nativeGen/Platform defines some data types enumerating
          the architectures and operating systems supported by the 
          native code generator.
        
        - DynFlags now keeps track of the current build platform, and 
          the PositionIndependentCode module uses this to decide what
          to do instead of relying of #ifdefs.
        
        - It's not totally retargetable yet. Some info info about the
          build target is still hardwired, but I've tried to contain
          most of it to a single module, TargetRegs.
        
        - Moved the SPILL and RELOAD instructions into LiveInstr.
        
        - Reg and RegClass now have their own modules, and are shared
          across all architectures.
      b04a210e
  23. 05 Feb, 2009 2 commits
  24. 04 Feb, 2009 2 commits
  25. 05 Feb, 2009 1 commit
  26. 03 Feb, 2009 1 commit