MachCodeGen.hs 149 KB
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-----------------------------------------------------------------------------
--
-- Generating machine code (instruction selection)
--
-- (c) The University of Glasgow 1996-2004
--
-----------------------------------------------------------------------------

-- This is a big module, but, if you pay attention to
-- (a) the sectioning, (b) the type signatures, and
-- (c) the #if blah_TARGET_ARCH} things, the
-- structure should not be too overwhelming.

module MachCodeGen ( cmmTopCodeGen, InstrBlock ) where

#include "HsVersions.h"
#include "nativeGen/NCG.h"
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#include "MachDeps.h"
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-- NCG stuff:
import MachInstrs
import MachRegs
import NCGMonad
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import PositionIndependentCode ( cmmMakeDynamicReference, initializePicBase )
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-- Our intermediate code:
import PprCmm		( pprExpr )
import Cmm
import MachOp
import CLabel

-- The rest:
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import StaticFlags	( opt_PIC )
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import ForeignCall	( CCallConv(..) )
import OrdList
import Pretty
import Outputable
import FastString
import FastTypes	( isFastTrue )
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import Constants	( wORD_SIZE )
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#ifdef DEBUG
import Outputable	( assertPanic )
import TRACE		( trace )
#endif

import Control.Monad	( mapAndUnzipM )
import Maybe		( fromJust )
import DATA_BITS
import DATA_WORD

-- -----------------------------------------------------------------------------
-- Top-level of the instruction selector

-- | 'InstrBlock's are the insn sequences generated by the insn selectors.
-- They are really trees of insns to facilitate fast appending, where a
-- left-to-right traversal (pre-order?) yields the insns in the correct
-- order.

type InstrBlock = OrdList Instr

cmmTopCodeGen :: CmmTop -> NatM [NatCmmTop]
cmmTopCodeGen (CmmProc info lab params blocks) = do
  (nat_blocks,statics) <- mapAndUnzipM basicBlockCodeGen blocks
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  picBaseMb <- getPicBaseMaybeNat
  let proc = CmmProc info lab params (concat nat_blocks)
      tops = proc : concat statics
  case picBaseMb of
      Just picBase -> initializePicBase picBase tops
      Nothing -> return tops
  
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cmmTopCodeGen (CmmData sec dat) = do
  return [CmmData sec dat]  -- no translation, we just use CmmStatic

basicBlockCodeGen :: CmmBasicBlock -> NatM ([NatBasicBlock],[NatCmmTop])
basicBlockCodeGen (BasicBlock id stmts) = do
  instrs <- stmtsToInstrs stmts
  -- code generation may introduce new basic block boundaries, which
  -- are indicated by the NEWBLOCK instruction.  We must split up the
  -- instruction stream into basic blocks again.  Also, we extract
  -- LDATAs here too.
  let
	(top,other_blocks,statics) = foldrOL mkBlocks ([],[],[]) instrs
	
	mkBlocks (NEWBLOCK id) (instrs,blocks,statics) 
	  = ([], BasicBlock id instrs : blocks, statics)
	mkBlocks (LDATA sec dat) (instrs,blocks,statics) 
	  = (instrs, blocks, CmmData sec dat:statics)
	mkBlocks instr (instrs,blocks,statics)
	  = (instr:instrs, blocks, statics)
  -- in
  return (BasicBlock id top : other_blocks, statics)

stmtsToInstrs :: [CmmStmt] -> NatM InstrBlock
stmtsToInstrs stmts
   = do instrss <- mapM stmtToInstrs stmts
        return (concatOL instrss)

stmtToInstrs :: CmmStmt -> NatM InstrBlock
stmtToInstrs stmt = case stmt of
    CmmNop	   -> return nilOL
    CmmComment s   -> return (unitOL (COMMENT s))

    CmmAssign reg src
      | isFloatingRep kind -> assignReg_FltCode kind reg src
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#if WORD_SIZE_IN_BITS==32
      | kind == I64 	   -> assignReg_I64Code      reg src
#endif
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      | otherwise	   -> assignReg_IntCode kind reg src
	where kind = cmmRegRep reg

    CmmStore addr src
      | isFloatingRep kind -> assignMem_FltCode kind addr src
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#if WORD_SIZE_IN_BITS==32
      | kind == I64 	 -> assignMem_I64Code      addr src
#endif
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      | otherwise	 -> assignMem_IntCode kind addr src
	where kind = cmmExprRep src

    CmmCall target result_regs args vols
       -> genCCall target result_regs args vols

    CmmBranch id	  -> genBranch id
    CmmCondBranch arg id  -> genCondJump id arg
    CmmSwitch arg ids     -> genSwitch arg ids
    CmmJump arg params	  -> genJump arg

-- -----------------------------------------------------------------------------
-- General things for putting together code sequences

-- Expand CmmRegOff.  ToDo: should we do it this way around, or convert
-- CmmExprs into CmmRegOff?
mangleIndexTree :: CmmExpr -> CmmExpr
mangleIndexTree (CmmRegOff reg off)
  = CmmMachOp (MO_Add rep) [CmmReg reg, CmmLit (CmmInt (fromIntegral off) rep)]
  where rep = cmmRegRep reg

-- -----------------------------------------------------------------------------
--  Code gen for 64-bit arithmetic on 32-bit platforms

{-
Simple support for generating 64-bit code (ie, 64 bit values and 64
bit assignments) on 32-bit platforms.  Unlike the main code generator
we merely shoot for generating working code as simply as possible, and
pay little attention to code quality.  Specifically, there is no
attempt to deal cleverly with the fixed-vs-floating register
distinction; all values are generated into (pairs of) floating
registers, even if this would mean some redundant reg-reg moves as a
result.  Only one of the VRegUniques is returned, since it will be
of the VRegUniqueLo form, and the upper-half VReg can be determined
by applying getHiVRegFromLo to it.
-}

data ChildCode64 	-- a.k.a "Register64"
   = ChildCode64 
        InstrBlock 	-- code
        Reg	 	-- the lower 32-bit temporary which contains the
			-- result; use getHiVRegFromLo to find the other
			-- VRegUnique.  Rules of this simplified insn
			-- selection game are therefore that the returned
			-- Reg may be modified

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#if WORD_SIZE_IN_BITS==32
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assignMem_I64Code :: CmmExpr -> CmmExpr -> NatM InstrBlock
assignReg_I64Code :: CmmReg  -> CmmExpr -> NatM InstrBlock
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#endif

#ifndef x86_64_TARGET_ARCH
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iselExpr64        :: CmmExpr -> NatM ChildCode64
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#endif
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-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

#if i386_TARGET_ARCH

assignMem_I64Code addrTree valueTree = do
  Amode addr addr_code <- getAmode addrTree
  ChildCode64 vcode rlo <- iselExpr64 valueTree
  let 
        rhi = getHiVRegFromLo rlo

        -- Little-endian store
        mov_lo = MOV I32 (OpReg rlo) (OpAddr addr)
        mov_hi = MOV I32 (OpReg rhi) (OpAddr (fromJust (addrOffset addr 4)))
  -- in
  return (vcode `appOL` addr_code `snocOL` mov_lo `snocOL` mov_hi)


assignReg_I64Code (CmmLocal (LocalReg u_dst pk)) valueTree = do
   ChildCode64 vcode r_src_lo <- iselExpr64 valueTree
   let 
         r_dst_lo = mkVReg u_dst I32
         r_dst_hi = getHiVRegFromLo r_dst_lo
         r_src_hi = getHiVRegFromLo r_src_lo
         mov_lo = MOV I32 (OpReg r_src_lo) (OpReg r_dst_lo)
         mov_hi = MOV I32 (OpReg r_src_hi) (OpReg r_dst_hi)
   -- in
   return (
        vcode `snocOL` mov_lo `snocOL` mov_hi
     )

assignReg_I64Code lvalue valueTree
   = panic "assignReg_I64Code(i386): invalid lvalue"

------------

iselExpr64 (CmmLit (CmmInt i _)) = do
  (rlo,rhi) <- getNewRegPairNat I32
  let
	r = fromIntegral (fromIntegral i :: Word32)
	q = fromIntegral ((fromIntegral i `shiftR` 32) :: Word32)
	code = toOL [
		MOV I32 (OpImm (ImmInteger r)) (OpReg rlo),
		MOV I32 (OpImm (ImmInteger q)) (OpReg rhi)
		]
  -- in
  return (ChildCode64 code rlo)

iselExpr64 (CmmLoad addrTree I64) = do
   Amode addr addr_code <- getAmode addrTree
   (rlo,rhi) <- getNewRegPairNat I32
   let 
        mov_lo = MOV I32 (OpAddr addr) (OpReg rlo)
        mov_hi = MOV I32 (OpAddr (fromJust (addrOffset addr 4))) (OpReg rhi)
   -- in
   return (
            ChildCode64 (addr_code `snocOL` mov_lo `snocOL` mov_hi) 
                        rlo
     )

iselExpr64 (CmmReg (CmmLocal (LocalReg vu I64)))
   = return (ChildCode64 nilOL (mkVReg vu I32))
         
-- we handle addition, but rather badly
iselExpr64 (CmmMachOp (MO_Add _) [e1, CmmLit (CmmInt i _)]) = do
   ChildCode64 code1 r1lo <- iselExpr64 e1
   (rlo,rhi) <- getNewRegPairNat I32
   let
	r = fromIntegral (fromIntegral i :: Word32)
	q = fromIntegral ((fromIntegral i `shiftR` 32) :: Word32)
	r1hi = getHiVRegFromLo r1lo
	code =  code1 `appOL`
		toOL [ MOV I32 (OpReg r1lo) (OpReg rlo),
		       ADD I32 (OpImm (ImmInteger r)) (OpReg rlo),
		       MOV I32 (OpReg r1hi) (OpReg rhi),
		       ADC I32 (OpImm (ImmInteger q)) (OpReg rhi) ]
   -- in
   return (ChildCode64 code rlo)

iselExpr64 (CmmMachOp (MO_Add _) [e1,e2]) = do
   ChildCode64 code1 r1lo <- iselExpr64 e1
   ChildCode64 code2 r2lo <- iselExpr64 e2
   (rlo,rhi) <- getNewRegPairNat I32
   let
	r1hi = getHiVRegFromLo r1lo
	r2hi = getHiVRegFromLo r2lo
	code =  code1 `appOL`
		code2 `appOL`
		toOL [ MOV I32 (OpReg r1lo) (OpReg rlo),
		       ADD I32 (OpReg r2lo) (OpReg rlo),
		       MOV I32 (OpReg r1hi) (OpReg rhi),
		       ADC I32 (OpReg r2hi) (OpReg rhi) ]
   -- in
   return (ChildCode64 code rlo)

iselExpr64 expr
   = pprPanic "iselExpr64(i386)" (ppr expr)

#endif /* i386_TARGET_ARCH */

-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

#if sparc_TARGET_ARCH

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assignMem_I64Code addrTree valueTree = do
     Amode addr addr_code <- getAmode addrTree
     ChildCode64 vcode rlo <- iselExpr64 valueTree  
     (src, code) <- getSomeReg addrTree
     let 
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         rhi = getHiVRegFromLo rlo
         -- Big-endian store
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         mov_hi = ST I32 rhi (AddrRegImm src (ImmInt 0))
         mov_lo = ST I32 rlo (AddrRegImm src (ImmInt 4))
     return (vcode `appOL` code `snocOL` mov_hi `snocOL` mov_lo)
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assignReg_I64Code (CmmLocal (LocalReg u_dst pk)) valueTree = do
     ChildCode64 vcode r_src_lo <- iselExpr64 valueTree    
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     let 
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         r_dst_lo = mkVReg u_dst pk
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         r_dst_hi = getHiVRegFromLo r_dst_lo
         r_src_hi = getHiVRegFromLo r_src_lo
         mov_lo = mkMOV r_src_lo r_dst_lo
         mov_hi = mkMOV r_src_hi r_dst_hi
         mkMOV sreg dreg = OR False g0 (RIReg sreg) dreg
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     return (vcode `snocOL` mov_hi `snocOL` mov_lo)
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assignReg_I64Code lvalue valueTree
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   = panic "assignReg_I64Code(sparc): invalid lvalue"
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-- Don't delete this -- it's very handy for debugging.
--iselExpr64 expr 
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--   | trace ("iselExpr64: " ++ showSDoc (ppr expr)) False
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--   = panic "iselExpr64(???)"

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iselExpr64 (CmmLoad addrTree I64) = do
     Amode (AddrRegReg r1 r2) addr_code <- getAmode addrTree
     rlo <- getNewRegNat I32
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     let rhi = getHiVRegFromLo rlo
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         mov_hi = LD I32 (AddrRegImm r1 (ImmInt 0)) rhi
         mov_lo = LD I32 (AddrRegImm r1 (ImmInt 4)) rlo
     return (
            ChildCode64 (addr_code `snocOL` mov_hi `snocOL` mov_lo) 
                         rlo
          )
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iselExpr64 (CmmReg (CmmLocal (LocalReg uq I64))) = do
     r_dst_lo <-  getNewRegNat I32
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     let r_dst_hi = getHiVRegFromLo r_dst_lo
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         r_src_lo = mkVReg uq I32
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         r_src_hi = getHiVRegFromLo r_src_lo
         mov_lo = mkMOV r_src_lo r_dst_lo
         mov_hi = mkMOV r_src_hi r_dst_hi
         mkMOV sreg dreg = OR False g0 (RIReg sreg) dreg
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     return (
            ChildCode64 (toOL [mov_hi, mov_lo]) r_dst_lo
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         )

iselExpr64 expr
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   = pprPanic "iselExpr64(sparc)" (ppr expr)
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#endif /* sparc_TARGET_ARCH */

-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

#if powerpc_TARGET_ARCH

getI64Amodes :: CmmExpr -> NatM (AddrMode, AddrMode, InstrBlock)
getI64Amodes addrTree = do
    Amode hi_addr addr_code <- getAmode addrTree
    case addrOffset hi_addr 4 of
        Just lo_addr -> return (hi_addr, lo_addr, addr_code)
        Nothing      -> do (hi_ptr, code) <- getSomeReg addrTree
                           return (AddrRegImm hi_ptr (ImmInt 0),
                                   AddrRegImm hi_ptr (ImmInt 4),
                                   code)

assignMem_I64Code addrTree valueTree = do
        (hi_addr, lo_addr, addr_code) <- getI64Amodes addrTree
	ChildCode64 vcode rlo <- iselExpr64 valueTree
	let 
		rhi = getHiVRegFromLo rlo

		-- Big-endian store
		mov_hi = ST I32 rhi hi_addr
		mov_lo = ST I32 rlo lo_addr
	-- in
	return (vcode `appOL` addr_code `snocOL` mov_lo `snocOL` mov_hi)

assignReg_I64Code (CmmLocal (LocalReg u_dst pk)) valueTree = do
   ChildCode64 vcode r_src_lo <- iselExpr64 valueTree
   let 
         r_dst_lo = mkVReg u_dst I32
         r_dst_hi = getHiVRegFromLo r_dst_lo
         r_src_hi = getHiVRegFromLo r_src_lo
         mov_lo = MR r_dst_lo r_src_lo
         mov_hi = MR r_dst_hi r_src_hi
   -- in
   return (
        vcode `snocOL` mov_lo `snocOL` mov_hi
     )

assignReg_I64Code lvalue valueTree
   = panic "assignReg_I64Code(powerpc): invalid lvalue"


-- Don't delete this -- it's very handy for debugging.
--iselExpr64 expr 
--   | trace ("iselExpr64: " ++ showSDoc (pprCmmExpr expr)) False
--   = panic "iselExpr64(???)"

iselExpr64 (CmmLoad addrTree I64) = do
    (hi_addr, lo_addr, addr_code) <- getI64Amodes addrTree
    (rlo, rhi) <- getNewRegPairNat I32
    let mov_hi = LD I32 rhi hi_addr
        mov_lo = LD I32 rlo lo_addr
    return $ ChildCode64 (addr_code `snocOL` mov_lo `snocOL` mov_hi) 
                         rlo

iselExpr64 (CmmReg (CmmLocal (LocalReg vu I64)))
   = return (ChildCode64 nilOL (mkVReg vu I32))

iselExpr64 (CmmLit (CmmInt i _)) = do
  (rlo,rhi) <- getNewRegPairNat I32
  let
	half0 = fromIntegral (fromIntegral i :: Word16)
	half1 = fromIntegral ((fromIntegral i `shiftR` 16) :: Word16)
	half2 = fromIntegral ((fromIntegral i `shiftR` 32) :: Word16)
	half3 = fromIntegral ((fromIntegral i `shiftR` 48) :: Word16)
	
	code = toOL [
		LIS rlo (ImmInt half1),
		OR rlo rlo (RIImm $ ImmInt half0),
		LIS rhi (ImmInt half3),
		OR rlo rlo (RIImm $ ImmInt half2)
		]
  -- in
  return (ChildCode64 code rlo)

iselExpr64 (CmmMachOp (MO_Add _) [e1,e2]) = do
   ChildCode64 code1 r1lo <- iselExpr64 e1
   ChildCode64 code2 r2lo <- iselExpr64 e2
   (rlo,rhi) <- getNewRegPairNat I32
   let
	r1hi = getHiVRegFromLo r1lo
	r2hi = getHiVRegFromLo r2lo
	code =  code1 `appOL`
		code2 `appOL`
		toOL [ ADDC rlo r1lo r2lo,
		       ADDE rhi r1hi r2hi ]
   -- in
   return (ChildCode64 code rlo)

iselExpr64 expr
   = pprPanic "iselExpr64(powerpc)" (ppr expr)

#endif /* powerpc_TARGET_ARCH */


-- -----------------------------------------------------------------------------
-- The 'Register' type

-- 'Register's passed up the tree.  If the stix code forces the register
-- to live in a pre-decided machine register, it comes out as @Fixed@;
-- otherwise, it comes out as @Any@, and the parent can decide which
-- register to put it in.

data Register
  = Fixed   MachRep Reg InstrBlock
  | Any	    MachRep (Reg -> InstrBlock)

swizzleRegisterRep :: Register -> MachRep -> Register
swizzleRegisterRep (Fixed _ reg code) rep = Fixed rep reg code
swizzleRegisterRep (Any _ codefn)     rep = Any rep codefn


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-- -----------------------------------------------------------------------------
-- Utils based on getRegister, below

-- The dual to getAnyReg: compute an expression into a register, but
-- we don't mind which one it is.
getSomeReg :: CmmExpr -> NatM (Reg, InstrBlock)
getSomeReg expr = do
  r <- getRegister expr
  case r of
    Any rep code -> do
	tmp <- getNewRegNat rep
	return (tmp, code tmp)
    Fixed _ reg code -> 
	return (reg, code)

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-- -----------------------------------------------------------------------------
-- Grab the Reg for a CmmReg

getRegisterReg :: CmmReg -> Reg

getRegisterReg (CmmLocal (LocalReg u pk))
  = mkVReg u pk

getRegisterReg (CmmGlobal mid)
  = case get_GlobalReg_reg_or_addr mid of
       Left (RealReg rrno) -> RealReg rrno
       _other -> pprPanic "getRegisterReg-memory" (ppr $ CmmGlobal mid)
          -- By this stage, the only MagicIds remaining should be the
          -- ones which map to a real machine register on this
          -- platform.  Hence ...


-- -----------------------------------------------------------------------------
-- Generate code to get a subtree into a Register

-- Don't delete this -- it's very handy for debugging.
--getRegister expr 
--   | trace ("getRegister: " ++ showSDoc (pprCmmExpr expr)) False
--   = panic "getRegister(???)"

getRegister :: CmmExpr -> NatM Register

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getRegister (CmmReg (CmmGlobal PicBaseReg))
  = do
      reg <- getPicBaseNat wordRep
      return (Fixed wordRep reg nilOL)

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getRegister (CmmReg reg) 
  = return (Fixed (cmmRegRep reg) (getRegisterReg reg) nilOL)

getRegister tree@(CmmRegOff _ _) 
  = getRegister (mangleIndexTree tree)

-- end of machine-"independent" bit; here we go on the rest...

#if alpha_TARGET_ARCH

getRegister (StDouble d)
  = getBlockIdNat 	    	    `thenNat` \ lbl ->
    getNewRegNat PtrRep    	    `thenNat` \ tmp ->
    let code dst = mkSeqInstrs [
	    LDATA RoDataSegment lbl [
		    DATA TF [ImmLab (rational d)]
		],
	    LDA tmp (AddrImm (ImmCLbl lbl)),
	    LD TF dst (AddrReg tmp)]
    in
    	return (Any F64 code)

getRegister (StPrim primop [x]) -- unary PrimOps
  = case primop of
      IntNegOp -> trivialUCode (NEG Q False) x

      NotOp    -> trivialUCode NOT x

      FloatNegOp  -> trivialUFCode FloatRep  (FNEG TF) x
      DoubleNegOp -> trivialUFCode F64 (FNEG TF) x

      OrdOp -> coerceIntCode IntRep x
      ChrOp -> chrCode x

      Float2IntOp  -> coerceFP2Int    x
      Int2FloatOp  -> coerceInt2FP pr x
      Double2IntOp -> coerceFP2Int    x
      Int2DoubleOp -> coerceInt2FP pr x

      Double2FloatOp -> coerceFltCode x
      Float2DoubleOp -> coerceFltCode x

      other_op -> getRegister (StCall fn CCallConv F64 [x])
	where
	  fn = case other_op of
		 FloatExpOp    -> FSLIT("exp")
		 FloatLogOp    -> FSLIT("log")
		 FloatSqrtOp   -> FSLIT("sqrt")
		 FloatSinOp    -> FSLIT("sin")
		 FloatCosOp    -> FSLIT("cos")
		 FloatTanOp    -> FSLIT("tan")
		 FloatAsinOp   -> FSLIT("asin")
		 FloatAcosOp   -> FSLIT("acos")
		 FloatAtanOp   -> FSLIT("atan")
		 FloatSinhOp   -> FSLIT("sinh")
		 FloatCoshOp   -> FSLIT("cosh")
		 FloatTanhOp   -> FSLIT("tanh")
		 DoubleExpOp   -> FSLIT("exp")
		 DoubleLogOp   -> FSLIT("log")
		 DoubleSqrtOp  -> FSLIT("sqrt")
		 DoubleSinOp   -> FSLIT("sin")
		 DoubleCosOp   -> FSLIT("cos")
		 DoubleTanOp   -> FSLIT("tan")
		 DoubleAsinOp  -> FSLIT("asin")
		 DoubleAcosOp  -> FSLIT("acos")
		 DoubleAtanOp  -> FSLIT("atan")
		 DoubleSinhOp  -> FSLIT("sinh")
		 DoubleCoshOp  -> FSLIT("cosh")
		 DoubleTanhOp  -> FSLIT("tanh")
  where
    pr = panic "MachCode.getRegister: no primrep needed for Alpha"

getRegister (StPrim primop [x, y]) -- dyadic PrimOps
  = case primop of
      CharGtOp -> trivialCode (CMP LTT) y x
      CharGeOp -> trivialCode (CMP LE) y x
      CharEqOp -> trivialCode (CMP EQQ) x y
      CharNeOp -> int_NE_code x y
      CharLtOp -> trivialCode (CMP LTT) x y
      CharLeOp -> trivialCode (CMP LE) x y

      IntGtOp  -> trivialCode (CMP LTT) y x
      IntGeOp  -> trivialCode (CMP LE) y x
      IntEqOp  -> trivialCode (CMP EQQ) x y
      IntNeOp  -> int_NE_code x y
      IntLtOp  -> trivialCode (CMP LTT) x y
      IntLeOp  -> trivialCode (CMP LE) x y

      WordGtOp -> trivialCode (CMP ULT) y x
      WordGeOp -> trivialCode (CMP ULE) x y
      WordEqOp -> trivialCode (CMP EQQ)  x y
      WordNeOp -> int_NE_code x y
      WordLtOp -> trivialCode (CMP ULT) x y
      WordLeOp -> trivialCode (CMP ULE) x y

      AddrGtOp -> trivialCode (CMP ULT) y x
      AddrGeOp -> trivialCode (CMP ULE) y x
      AddrEqOp -> trivialCode (CMP EQQ)  x y
      AddrNeOp -> int_NE_code x y
      AddrLtOp -> trivialCode (CMP ULT) x y
      AddrLeOp -> trivialCode (CMP ULE) x y
	
      FloatGtOp -> cmpF_code (FCMP TF LE) EQQ x y
      FloatGeOp -> cmpF_code (FCMP TF LTT) EQQ x y
      FloatEqOp -> cmpF_code (FCMP TF EQQ) NE x y
      FloatNeOp -> cmpF_code (FCMP TF EQQ) EQQ x y
      FloatLtOp -> cmpF_code (FCMP TF LTT) NE x y
      FloatLeOp -> cmpF_code (FCMP TF LE) NE x y

      DoubleGtOp -> cmpF_code (FCMP TF LE) EQQ x y
      DoubleGeOp -> cmpF_code (FCMP TF LTT) EQQ x y
      DoubleEqOp -> cmpF_code (FCMP TF EQQ) NE x y
      DoubleNeOp -> cmpF_code (FCMP TF EQQ) EQQ x y
      DoubleLtOp -> cmpF_code (FCMP TF LTT) NE x y
      DoubleLeOp -> cmpF_code (FCMP TF LE) NE x y

      IntAddOp  -> trivialCode (ADD Q False) x y
      IntSubOp  -> trivialCode (SUB Q False) x y
      IntMulOp  -> trivialCode (MUL Q False) x y
      IntQuotOp -> trivialCode (DIV Q False) x y
      IntRemOp  -> trivialCode (REM Q False) x y

      WordAddOp  -> trivialCode (ADD Q False) x y
      WordSubOp  -> trivialCode (SUB Q False) x y
      WordMulOp  -> trivialCode (MUL Q False) x y
      WordQuotOp -> trivialCode (DIV Q True) x y
      WordRemOp  -> trivialCode (REM Q True) x y

      FloatAddOp -> trivialFCode  FloatRep (FADD TF) x y
      FloatSubOp -> trivialFCode  FloatRep (FSUB TF) x y
      FloatMulOp -> trivialFCode  FloatRep (FMUL TF) x y
      FloatDivOp -> trivialFCode  FloatRep (FDIV TF) x y

      DoubleAddOp -> trivialFCode  F64 (FADD TF) x y
      DoubleSubOp -> trivialFCode  F64 (FSUB TF) x y
      DoubleMulOp -> trivialFCode  F64 (FMUL TF) x y
      DoubleDivOp -> trivialFCode  F64 (FDIV TF) x y

      AddrAddOp  -> trivialCode (ADD Q False) x y
      AddrSubOp  -> trivialCode (SUB Q False) x y
      AddrRemOp  -> trivialCode (REM Q True) x y

      AndOp  -> trivialCode AND x y
      OrOp   -> trivialCode OR  x y
      XorOp  -> trivialCode XOR x y
      SllOp  -> trivialCode SLL x y
      SrlOp  -> trivialCode SRL x y

      ISllOp -> trivialCode SLL x y -- was: panic "AlphaGen:isll"
      ISraOp -> trivialCode SRA x y -- was: panic "AlphaGen:isra"
      ISrlOp -> trivialCode SRL x y -- was: panic "AlphaGen:isrl"

      FloatPowerOp  -> getRegister (StCall FSLIT("pow") CCallConv F64 [x,y])
      DoublePowerOp -> getRegister (StCall FSLIT("pow") CCallConv F64 [x,y])
  where
    {- ------------------------------------------------------------
	Some bizarre special code for getting condition codes into
	registers.  Integer non-equality is a test for equality
	followed by an XOR with 1.  (Integer comparisons always set
	the result register to 0 or 1.)  Floating point comparisons of
	any kind leave the result in a floating point register, so we
	need to wrangle an integer register out of things.
    -}
    int_NE_code :: StixTree -> StixTree -> NatM Register

    int_NE_code x y
      = trivialCode (CMP EQQ) x y	`thenNat` \ register ->
	getNewRegNat IntRep		`thenNat` \ tmp ->
	let
	    code = registerCode register tmp
	    src  = registerName register tmp
	    code__2 dst = code . mkSeqInstr (XOR src (RIImm (ImmInt 1)) dst)
	in
	return (Any IntRep code__2)

    {- ------------------------------------------------------------
	Comments for int_NE_code also apply to cmpF_code
    -}
    cmpF_code
	:: (Reg -> Reg -> Reg -> Instr)
	-> Cond
	-> StixTree -> StixTree
	-> NatM Register

    cmpF_code instr cond x y
      = trivialFCode pr instr x y	`thenNat` \ register ->
	getNewRegNat F64		`thenNat` \ tmp ->
	getBlockIdNat			`thenNat` \ lbl ->
	let
	    code = registerCode register tmp
	    result  = registerName register tmp

	    code__2 dst = code . mkSeqInstrs [
		OR zeroh (RIImm (ImmInt 1)) dst,
		BF cond  result (ImmCLbl lbl),
		OR zeroh (RIReg zeroh) dst,
		NEWBLOCK lbl]
	in
	return (Any IntRep code__2)
      where
	pr = panic "trivialU?FCode: does not use PrimRep on Alpha"
      ------------------------------------------------------------

getRegister (CmmLoad pk mem)
  = getAmode mem    	    	    `thenNat` \ amode ->
    let
    	code = amodeCode amode
    	src   = amodeAddr amode
    	size = primRepToSize pk
    	code__2 dst = code . mkSeqInstr (LD size dst src)
    in
    return (Any pk code__2)

getRegister (StInt i)
  | fits8Bits i
  = let
    	code dst = mkSeqInstr (OR zeroh (RIImm src) dst)
    in
    return (Any IntRep code)
  | otherwise
  = let
    	code dst = mkSeqInstr (LDI Q dst src)
    in
    return (Any IntRep code)
  where
    src = ImmInt (fromInteger i)

getRegister leaf
  | isJust imm
  = let
    	code dst = mkSeqInstr (LDA dst (AddrImm imm__2))
    in
    return (Any PtrRep code)
  where
    imm = maybeImm leaf
    imm__2 = case imm of Just x -> x

#endif /* alpha_TARGET_ARCH */

-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

#if i386_TARGET_ARCH

getRegister (CmmLit (CmmFloat f F32)) = do
    lbl <- getNewLabelNat
738
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740
    dynRef <- cmmMakeDynamicReference addImportNat False lbl
    Amode addr addr_code <- getAmode dynRef
    let code dst =
741
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	    LDATA ReadOnlyData
			[CmmDataLabel lbl,
743
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			 CmmStaticLit (CmmFloat f F32)]
	    `consOL` (addr_code `snocOL`
	    GLD F32 addr dst)
746
747
748
749
750
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753
754
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760
    -- in
    return (Any F32 code)


getRegister (CmmLit (CmmFloat d F64))
  | d == 0.0
  = let code dst = unitOL (GLDZ dst)
    in  return (Any F64 code)

  | d == 1.0
  = let code dst = unitOL (GLD1 dst)
    in  return (Any F64 code)

  | otherwise = do
    lbl <- getNewLabelNat
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762
763
    dynRef <- cmmMakeDynamicReference addImportNat False lbl
    Amode addr addr_code <- getAmode dynRef
    let code dst =
764
765
	    LDATA ReadOnlyData
			[CmmDataLabel lbl,
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768
			 CmmStaticLit (CmmFloat d F64)]
	    `consOL` (addr_code `snocOL`
	    GLD F64 addr dst)
769
770
771
    -- in
    return (Any F64 code)

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#endif /* i386_TARGET_ARCH */

#if x86_64_TARGET_ARCH

getRegister (CmmLit (CmmFloat 0.0 rep)) = do
   let code dst = unitOL  (XOR rep (OpReg dst) (OpReg dst))
	-- I don't know why there are xorpd, xorps, and pxor instructions.
	-- They all appear to do the same thing --SDM
   return (Any rep code)

getRegister (CmmLit (CmmFloat f rep)) = do
    lbl <- getNewLabelNat
    let code dst = toOL [
	    LDATA ReadOnlyData
			[CmmDataLabel lbl,
			 CmmStaticLit (CmmFloat f rep)],
788
	    MOV rep (OpAddr (ripRel (ImmCLbl lbl))) (OpReg dst)
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	    ]
    -- in
    return (Any rep code)

#endif /* x86_64_TARGET_ARCH */

#if i386_TARGET_ARCH || x86_64_TARGET_ARCH
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-- catch simple cases of zero- or sign-extended load
getRegister (CmmMachOp (MO_U_Conv I8 I32) [CmmLoad addr _]) = do
  code <- intLoadCode (MOVZxL I8) addr
  return (Any I32 code)

getRegister (CmmMachOp (MO_S_Conv I8 I32) [CmmLoad addr _]) = do
  code <- intLoadCode (MOVSxL I8) addr
  return (Any I32 code)

getRegister (CmmMachOp (MO_U_Conv I16 I32) [CmmLoad addr _]) = do
  code <- intLoadCode (MOVZxL I16) addr
  return (Any I32 code)

getRegister (CmmMachOp (MO_S_Conv I16 I32) [CmmLoad addr _]) = do
  code <- intLoadCode (MOVSxL I16) addr
  return (Any I32 code)

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#endif

#if x86_64_TARGET_ARCH

-- catch simple cases of zero- or sign-extended load
getRegister (CmmMachOp (MO_U_Conv I8 I64) [CmmLoad addr _]) = do
  code <- intLoadCode (MOVZxL I8) addr
  return (Any I64 code)

getRegister (CmmMachOp (MO_S_Conv I8 I64) [CmmLoad addr _]) = do
  code <- intLoadCode (MOVSxL I8) addr
  return (Any I64 code)

getRegister (CmmMachOp (MO_U_Conv I16 I64) [CmmLoad addr _]) = do
  code <- intLoadCode (MOVZxL I16) addr
  return (Any I64 code)

getRegister (CmmMachOp (MO_S_Conv I16 I64) [CmmLoad addr _]) = do
  code <- intLoadCode (MOVSxL I16) addr
  return (Any I64 code)

getRegister (CmmMachOp (MO_U_Conv I32 I64) [CmmLoad addr _]) = do
  code <- intLoadCode (MOV I32) addr -- 32-bit loads zero-extend
  return (Any I64 code)

getRegister (CmmMachOp (MO_S_Conv I32 I64) [CmmLoad addr _]) = do
  code <- intLoadCode (MOVSxL I32) addr
  return (Any I64 code)

#endif

#if x86_64_TARGET_ARCH
getRegister (CmmMachOp (MO_S_Neg F32) [x]) = do
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  x_code <- getAnyReg x
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  lbl <- getNewLabelNat
  let
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    code dst = x_code dst `appOL` toOL [
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	-- This is how gcc does it, so it can't be that bad:
	LDATA ReadOnlyData16 [
		CmmAlign 16,
		CmmDataLabel lbl,
		CmmStaticLit (CmmInt 0x80000000 I32),
		CmmStaticLit (CmmInt 0 I32),
		CmmStaticLit (CmmInt 0 I32),
		CmmStaticLit (CmmInt 0 I32)
	],
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	XOR F32 (OpAddr (ripRel (ImmCLbl lbl))) (OpReg dst)
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		-- xorps, so we need the 128-bit constant
		-- ToDo: rip-relative
	]
  --
  return (Any F32 code)

getRegister (CmmMachOp (MO_S_Neg F64) [x]) = do
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  x_code <- getAnyReg x
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  lbl <- getNewLabelNat
  let
	-- This is how gcc does it, so it can't be that bad:
872
    code dst = x_code dst `appOL` toOL [
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	LDATA ReadOnlyData16 [
		CmmAlign 16,
		CmmDataLabel lbl,
		CmmStaticLit (CmmInt 0x8000000000000000 I64),
		CmmStaticLit (CmmInt 0 I64)
	],
		-- gcc puts an unpck here.  Wonder if we need it.
880
	XOR F64 (OpAddr (ripRel (ImmCLbl lbl))) (OpReg dst)
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		-- xorpd, so we need the 128-bit constant
	]
  --
  return (Any F64 code)
#endif

#if i386_TARGET_ARCH || x86_64_TARGET_ARCH
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getRegister (CmmMachOp mop [x]) -- unary MachOps
  = case mop of
891
#if i386_TARGET_ARCH
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893
      MO_S_Neg F32 -> trivialUFCode F32 (GNEG F32) x
      MO_S_Neg F64 -> trivialUFCode F64 (GNEG F64) x
894
#endif
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      MO_S_Neg rep -> trivialUCode rep (NEGI rep) x
      MO_Not rep   -> trivialUCode rep (NOT  rep) x

      -- Nop conversions
      -- TODO: these are only nops if the arg is not a fixed register that
      -- can't be byte-addressed.
      MO_U_Conv I32 I8  -> conversionNop I32 x
      MO_S_Conv I32 I8  -> conversionNop I32 x
      MO_U_Conv I16 I8  -> conversionNop I16 x
      MO_S_Conv I16 I8  -> conversionNop I16 x
      MO_U_Conv I32 I16 -> conversionNop I32 x
      MO_S_Conv I32 I16 -> conversionNop I32 x
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#if x86_64_TARGET_ARCH
      MO_U_Conv I64 I32 -> conversionNop I64 x
      MO_S_Conv I64 I32 -> conversionNop I64 x
      MO_U_Conv I64 I16 -> conversionNop I64 x
      MO_S_Conv I64 I16 -> conversionNop I64 x
      MO_U_Conv I64 I8  -> conversionNop I64 x
      MO_S_Conv I64 I8  -> conversionNop I64 x
#endif

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      MO_U_Conv rep1 rep2 | rep1 == rep2 -> conversionNop rep1 x
      MO_S_Conv rep1 rep2 | rep1 == rep2 -> conversionNop rep1 x

      -- widenings
      MO_U_Conv I8  I32 -> integerExtend I8  I32 MOVZxL x
      MO_U_Conv I16 I32 -> integerExtend I16 I32 MOVZxL x
      MO_U_Conv I8  I16 -> integerExtend I8  I16 MOVZxL x

      MO_S_Conv I8  I32 -> integerExtend I8  I32 MOVSxL x
      MO_S_Conv I16 I32 -> integerExtend I16 I32 MOVSxL x
      MO_S_Conv I8  I16 -> integerExtend I8  I16 MOVSxL x

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#if x86_64_TARGET_ARCH
      MO_U_Conv I8  I64 -> integerExtend I8  I64 MOVZxL x
      MO_U_Conv I16 I64 -> integerExtend I16 I64 MOVZxL x
      MO_U_Conv I32 I64 -> integerExtend I32 I64 MOVZxL x
      MO_S_Conv I8  I64 -> integerExtend I8  I64 MOVSxL x
      MO_S_Conv I16 I64 -> integerExtend I16 I64 MOVSxL x
      MO_S_Conv I32 I64 -> integerExtend I32 I64 MOVSxL x
	-- for 32-to-64 bit zero extension, amd64 uses an ordinary movl.
	-- However, we don't want the register allocator to throw it
	-- away as an unnecessary reg-to-reg move, so we keep it in
	-- the form of a movzl and print it as a movl later.
#endif

#if i386_TARGET_ARCH
943
944
      MO_S_Conv F32 F64 -> conversionNop F64 x
      MO_S_Conv F64 F32 -> conversionNop F32 x
945
946
947
948
949
#else
      MO_S_Conv F32 F64 -> coerceFP2FP F64 x
      MO_S_Conv F64 F32 -> coerceFP2FP F32 x
#endif

950
951
952
953
      MO_S_Conv from to
	| isFloatingRep from -> coerceFP2Int from to x
	| isFloatingRep to   -> coerceInt2FP from to x

954
      other -> pprPanic "getRegister" (pprMachOp mop)
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   where
	-- signed or unsigned extension.
	integerExtend from to instr expr = do
	    (reg,e_code) <- if from == I8 then getByteReg expr
					  else getSomeReg expr
	    let 
		code dst = 
		  e_code `snocOL`
		  instr from (OpReg reg) (OpReg dst)
	    return (Any to code)

        conversionNop new_rep expr
            = do e_code <- getRegister expr
                 return (swizzleRegisterRep e_code new_rep)


getRegister e@(CmmMachOp mop [x, y]) -- dyadic MachOps
  = ASSERT2(cmmExprRep x /= I8, pprExpr e)
    case mop of
      MO_Eq F32   -> condFltReg EQQ x y
      MO_Ne F32   -> condFltReg NE x y
      MO_S_Gt F32 -> condFltReg GTT x y
      MO_S_Ge F32 -> condFltReg GE x y
      MO_S_Lt F32 -> condFltReg LTT x y
      MO_S_Le F32 -> condFltReg LE x y

      MO_Eq F64   -> condFltReg EQQ x y
      MO_Ne F64   -> condFltReg NE x y
      MO_S_Gt F64 -> condFltReg GTT x y
      MO_S_Ge F64 -> condFltReg GE x y
      MO_S_Lt F64 -> condFltReg LTT x y
      MO_S_Le F64 -> condFltReg LE x y

      MO_Eq rep   -> condIntReg EQQ x y
      MO_Ne rep   -> condIntReg NE x y

      MO_S_Gt rep -> condIntReg GTT x y
      MO_S_Ge rep -> condIntReg GE x y
      MO_S_Lt rep -> condIntReg LTT x y
      MO_S_Le rep -> condIntReg LE x y

      MO_U_Gt rep -> condIntReg GU  x y
      MO_U_Ge rep -> condIntReg GEU x y
      MO_U_Lt rep -> condIntReg LU  x y
      MO_U_Le rep -> condIntReg LEU x y

1001
1002
1003
#if i386_TARGET_ARCH
      MO_Add F32 -> trivialFCode F32 GADD x y
      MO_Sub F32 -> trivialFCode F32 GSUB x y
1004
1005
1006
1007

      MO_Add F64 -> trivialFCode F64 GADD x y
      MO_Sub F64 -> trivialFCode F64 GSUB x y

1008
      MO_S_Quot F32 -> trivialFCode F32 GDIV x y
1009
      MO_S_Quot F64 -> trivialFCode F64 GDIV x y
1010
1011
1012
1013
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1015
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1017
1018
1019
1020
1021
#endif

#if x86_64_TARGET_ARCH
      MO_Add F32 -> trivialFCode F32 ADD x y
      MO_Sub F32 -> trivialFCode F32 SUB x y

      MO_Add F64 -> trivialFCode F64 ADD x y
      MO_Sub F64 -> trivialFCode F64 SUB x y

      MO_S_Quot F32 -> trivialFCode F32 FDIV x y
      MO_S_Quot F64 -> trivialFCode F64 FDIV x y
#endif
1022
1023
1024
1025
1026
1027
1028
1029
1030

      MO_Add rep -> add_code rep x y
      MO_Sub rep -> sub_code rep x y

      MO_S_Quot rep -> div_code rep True  True  x y
      MO_S_Rem  rep -> div_code rep True  False x y
      MO_U_Quot rep -> div_code rep False True  x y
      MO_U_Rem  rep -> div_code rep False False x y

1031
#if i386_TARGET_ARCH
1032
1033
      MO_Mul   F32 -> trivialFCode F32 GMUL x y
      MO_Mul   F64 -> trivialFCode F64 GMUL x y
1034
1035
1036
1037
1038
1039
1040
#endif

#if x86_64_TARGET_ARCH
      MO_Mul   F32 -> trivialFCode F32 MUL x y
      MO_Mul   F64 -> trivialFCode F64 MUL x y
#endif

1041
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1064
      MO_Mul   rep -> let op = IMUL rep in 
		      trivialCode rep op (Just op) x y

      MO_S_MulMayOflo rep -> imulMayOflo rep x y

      MO_And rep -> let op = AND rep in 
		    trivialCode rep op (Just op) x y
      MO_Or  rep -> let op = OR  rep in
		    trivialCode rep op (Just op) x y
      MO_Xor rep -> let op = XOR rep in
		    trivialCode rep op (Just op) x y

	{- Shift ops on x86s have constraints on their source, it
	   either has to be Imm, CL or 1
	    => trivialCode is not restrictive enough (sigh.)
	-}	   
      MO_Shl rep   -> shift_code rep (SHL rep) x y {-False-}
      MO_U_Shr rep -> shift_code rep (SHR rep) x y {-False-}
      MO_S_Shr rep -> shift_code rep (SAR rep) x y {-False-}

      other -> pprPanic "getRegister(x86) - binary CmmMachOp (1)" (pprMachOp mop)
  where
    --------------------
    imulMayOflo :: MachRep -> CmmExpr -> CmmExpr -> NatM Register
1065
    imulMayOflo rep a b = do
1066
         (a_reg, a_code) <- getNonClobberedReg a
1067
         b_code <- getAnyReg b
1068
         let 
1069
1070
1071
1072
1073
1074
	     shift_amt  = case rep of
			   I32 -> 31
			   I64 -> 63
			   _ -> panic "shift_amt"

             code = a_code `appOL` b_code eax `appOL`
1075
                        toOL [
1076
1077
1078
1079
1080
1081
			   IMUL2 rep (OpReg a_reg),   -- result in %edx:%eax
                           SAR rep (OpImm (ImmInt shift_amt)) (OpReg eax),
				-- sign extend lower part
                           SUB rep (OpReg edx) (OpReg eax)
				-- compare against upper
                           -- eax==0 if high part == sign extended low part
1082
1083
                        ]
         -- in
1084
	 return (Fixed rep eax code)
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115

    --------------------
    shift_code :: MachRep
	       -> (Operand -> Operand -> Instr)
	       -> CmmExpr
	       -> CmmExpr
	       -> NatM Register

    {- Case1: shift length as immediate -}
    shift_code rep instr x y@(CmmLit lit) = do
	  x_code <- getAnyReg x
	  let
	       code dst
		  = x_code dst `snocOL` 
		    instr (OpImm (litToImm lit)) (OpReg dst)
	  -- in
	  return (Any rep code)
        
    {- Case2: shift length is complex (non-immediate) -}
    shift_code rep instr x y{-amount-} = do
        (x_reg, x_code) <- getNonClobberedReg x
        y_code <- getAnyReg y
	let 
	   code = x_code `appOL`
		  y_code ecx `snocOL`
		  instr (OpReg ecx) (OpReg x_reg)
        -- in
        return (Fixed rep x_reg code)

    --------------------
    add_code :: MachRep -> CmmExpr -> CmmExpr -> NatM Register
1116
1117
    add_code rep x (CmmLit (CmmInt y _))
	| not (is64BitInteger y) = add_int rep x y
1118
1119
1120
1121
    add_code rep x y = trivialCode rep (ADD rep) (Just (ADD rep)) x y

    --------------------
    sub_code :: MachRep -> CmmExpr -> CmmExpr -> NatM Register
1122
1123
    sub_code rep x (CmmLit (CmmInt y _))
	| not (is64BitInteger (-y)) = add_int rep x (-y)
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
    sub_code rep x y = trivialCode rep (SUB rep) Nothing x y

    -- our three-operand add instruction:
    add_int rep x y = do
	(x_reg, x_code) <- getSomeReg x
	let
	    imm = ImmInt (fromInteger y)
	    code dst
               = x_code `snocOL`
		 LEA rep
1134
			(OpAddr (AddrBaseIndex (EABaseReg x_reg) EAIndexNone imm))
1135
1136
1137
1138
1139
1140
                        (OpReg dst)
	-- 
	return (Any rep code)

    ----------------------
    div_code rep signed quotient x y = do
1141
	   (y_op, y_code) <- getRegOrMem y -- cannot be clobbered
1142
1143
	   x_code <- getAnyReg x
	   let
1144
	     widen | signed    = CLTD rep
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
		   | otherwise = XOR rep (OpReg edx) (OpReg edx)

	     instr | signed    = IDIV
		   | otherwise = DIV

	     code = y_code `appOL`
		    x_code eax `appOL`
		    toOL [widen, instr rep y_op]

	     result | quotient  = eax
		    | otherwise = edx

	   -- in
           return (Fixed rep result code)


getRegister (CmmLoad mem pk)
  | isFloatingRep pk
  = do
    Amode src mem_code <- getAmode mem
    let
    	code dst = mem_code `snocOL` 
1167
1168
		   IF_ARCH_i386(GLD pk src dst,
			        MOV pk (OpAddr src) (OpReg dst))
1169
1170
1171
    --
    return (Any pk code)

1172
#if i386_TARGET_ARCH
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
getRegister (CmmLoad mem pk)
  | pk /= I64
  = do 
    code <- intLoadCode (instr pk) mem
    return (Any pk code)
  where
	instr I8  = MOVZxL pk
	instr I16 = MOV I16
	instr I32 = MOV I32
	-- we always zero-extend 8-bit loads, if we
	-- can't think of anything better.  This is because
	-- we can't guarantee access to an 8-bit variant of every register
	-- (esi and edi don't have 8-bit variants), so to make things
	-- simpler we do our 8-bit arithmetic with full 32-bit registers.
1187
1188
1189
1190
1191
1192
1193
1194
1195
#endif

#if x86_64_TARGET_ARCH
-- Simpler memory load code on x86_64
getRegister (CmmLoad mem pk)
  = do 
    code <- intLoadCode (MOV pk) mem
    return (Any pk code)
#endif
1196
1197
1198

getRegister (CmmLit (CmmInt 0 rep))
  = let
1199
1200
1201
	-- x86_64: 32-bit xor is one byte shorter, and zero-extends to 64 bits
	adj_rep = case rep of I64 -> I32; _ -> rep
	rep1 = IF_ARCH_i386( rep, adj_rep ) 
1202
    	code dst 
1203
           = unitOL (XOR rep1 (OpReg dst) (OpReg dst))
1204
1205
1206
    in
    	return (Any rep code)

1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
#if x86_64_TARGET_ARCH
  -- optimisation for loading small literals on x86_64: take advantage
  -- of the automatic zero-extension from 32 to 64 bits, because the 32-bit
  -- instruction forms are shorter.
getRegister (CmmLit lit) 
  | I64 <- cmmLitRep lit, not (isBigLit lit)
  = let 
	imm = litToImm lit
	code dst = unitOL (MOV I32 (OpImm imm) (OpReg dst))
    in
    	return (Any I64 code)
  where
   isBigLit (CmmInt i I64) = i < 0 || i > 0xffffffff
   isBigLit _ = False
	-- note1: not the same as is64BitLit, because that checks for
	-- signed literals that fit in 32 bits, but we want unsigned
	-- literals here.
	-- note2: all labels are small, because we're assuming the
	-- small memory model (see gcc docs, -mcmodel=small).
#endif

1228
1229
1230
1231
1232
1233
1234
1235
getRegister (CmmLit lit)
  = let 
	rep = cmmLitRep lit
	imm = litToImm lit
	code dst = unitOL (MOV rep (OpImm imm) (OpReg dst))
    in
    	return (Any rep code)

1236
getRegister other = pprPanic "getRegister(x86)" (ppr other)
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259


intLoadCode :: (Operand -> Operand -> Instr) -> CmmExpr
   -> NatM (Reg -> InstrBlock)
intLoadCode instr mem = do
  Amode src mem_code <- getAmode mem
  return (\dst -> mem_code `snocOL` instr (OpAddr src) (OpReg dst))

-- Compute an expression into *any* register, adding the appropriate
-- move instruction if necessary.
getAnyReg :: CmmExpr -> NatM (Reg -> InstrBlock)
getAnyReg expr = do
  r <- getRegister expr
  anyReg r

anyReg :: Register -> NatM (Reg -> InstrBlock)
anyReg (Any _ code)          = return code
anyReg (Fixed rep reg fcode) = return (\dst -> fcode `snocOL` reg2reg rep reg dst)

-- A bit like getSomeReg, but we want a reg that can be byte-addressed.
-- Fixed registers might not be byte-addressable, so we make sure we've
-- got a temporary, inserting an extra reg copy if necessary.
getByteReg :: CmmExpr -> NatM (Reg, InstrBlock)
1260
1261
1262
#if x86_64_TARGET_ARCH
getByteReg = getSomeReg -- all regs are byte-addressable on x86_64
#else
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
getByteReg expr = do
  r <- getRegister expr
  case r of
    Any rep code -> do
	tmp <- getNewRegNat rep
	return (tmp, code tmp)
    Fixed rep reg code 
	| isVirtualReg reg -> return (reg,code)
	| otherwise -> do
	    tmp <- getNewRegNat rep
	    return (tmp, code `snocOL` reg2reg rep reg tmp)
	-- ToDo: could optimise slightly by checking for byte-addressable
	-- real registers, but that will happen very rarely if at all.
1276
#endif
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296

-- Another variant: this time we want the result in a register that cannot
-- be modified by code to evaluate an arbitrary expression.
getNonClobberedReg :: CmmExpr -> NatM (Reg, InstrBlock)
getNonClobberedReg expr = do
  r <- getRegister expr
  case r of
    Any rep code -> do
	tmp <- getNewRegNat rep
	return (tmp, code tmp)
    Fixed rep reg code
	-- only free regs can be clobbered
	| RealReg rr <- reg, isFastTrue (freeReg rr) -> do
		tmp <- getNewRegNat rep
		return (tmp, code `snocOL` reg2reg rep reg tmp)
	| otherwise -> 
		return (reg, code)

reg2reg :: MachRep -> Reg -> Reg -> Instr
reg2reg rep src dst 
1297
#if i386_TARGET_ARCH
1298
  | isFloatingRep rep = GMOV src dst
1299
#endif
1300
1301
  | otherwise	      = MOV rep (OpReg src) (OpReg dst)

1302
#endif /* i386_TARGET_ARCH || x86_64_TARGET_ARCH */
1303
1304
1305
1306
1307

-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

#if sparc_TARGET_ARCH

1308
1309
getRegister (CmmLit (CmmFloat f F32)) = do
    lbl <- getNewLabelNat
1310
    let code dst = toOL [
1311
1312
1313
1314
1315
1316
	    LDATA ReadOnlyData
	                [CmmDataLabel lbl,
			 CmmStaticLit (CmmFloat f F32)],
	    SETHI (HI (ImmCLbl lbl)) dst,
	    LD F32 (AddrRegImm dst (LO (ImmCLbl lbl))) dst] 
    return (Any F32 code)
1317

1318
1319
getRegister (CmmLit (CmmFloat d F64)) = do
    lbl <- getNewLabelNat
1320
    let code dst = toOL [
1321
1322
1323
1324
1325
1326
	    LDATA ReadOnlyData
	                [CmmDataLabel lbl,
			 CmmStaticLit (CmmFloat d F64)],
	    SETHI (HI (ImmCLbl lbl)) dst,
	    LD F64 (AddrRegImm dst (LO (ImmCLbl lbl))) dst] 
    return (Any F64 code)
1327

1328
getRegister (CmmMachOp mop [x]) -- unary MachOps
1329
  = case mop of
1330
1331
      MO_S_Neg F32     -> trivialUFCode F32 (FNEG F32) x
      MO_S_Neg F64     -> trivialUFCode F64 (FNEG F64) x
1332

1333
1334
      MO_S_Neg rep     -> trivialUCode rep (SUB False False g0) x
      MO_Not rep       -> trivialUCode rep (XNOR False g0) x
1335

1336
      MO_U_Conv I32 I8 -> trivialCode I8 (AND False) x (CmmLit (CmmInt 255 I8))
1337

1338
1339
      MO_U_Conv F64 F32-> coerceDbl2Flt x
      MO_U_Conv F32 F64-> coerceFlt2Dbl x
1340

1341
1342
1343
1344
      MO_S_Conv F32 I32-> coerceFP2Int F32 I32 x
      MO_S_Conv I32 F32-> coerceInt2FP I32 F32 x
      MO_S_Conv F64 I32-> coerceFP2Int F64 I32 x
      MO_S_Conv I32 F64-> coerceInt2FP I32 F64 x
1345

1346
1347
1348
1349
1350
      -- Conversions which are a nop on sparc
      MO_U_Conv from to
	| from == to   -> conversionNop to   x
      MO_U_Conv I32 to -> conversionNop to   x
      MO_S_Conv I32 to -> conversionNop to   x
1351

1352
1353
1354
1355
1356
      -- widenings
      MO_U_Conv I8 I32  -> integerExtend False I8 I32  x
      MO_U_Conv I16 I32 -> integerExtend False I16 I32 x
      MO_U_Conv I8 I16  -> integerExtend False I8 I16  x
      MO_S_Conv I16 I32 -> integerExtend True I16 I32  x
1357

1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
      other_op -> panic "Unknown unary mach op"
    where
        -- XXX SLL/SRL?
        integerExtend signed from to expr = do
           (reg, e_code) <- getSomeReg expr
	   let
	       code dst =
		   e_code `snocOL` 
		   ((if signed then SRA else SRL)
		          reg (RIImm (ImmInt 0)) dst)
	   return (Any to code)
        conversionNop new_rep expr
            = do e_code <- getRegister expr
                 return (swizzleRegisterRep e_code new_rep)
1372

1373
1374
1375
1376
getRegister (CmmMachOp mop [x, y]) -- dyadic PrimOps
  = case mop of
      MO_Eq F32 -> condFltReg EQQ x y
      MO_Ne F32 -> condFltReg NE x y
1377

1378
1379
1380
1381
      MO_S_Gt F32 -> condFltReg GTT x y
      MO_S_Ge F32 -> condFltReg GE x y 
      MO_S_Lt F32 -> condFltReg LTT x y
      MO_S_Le F32 -> condFltReg LE x y
1382

1383
1384
      MO_Eq F64 -> condFltReg EQQ x y
      MO_Ne F64 -> condFltReg NE x y
1385

1386
1387
1388
1389
      MO_S_Gt F64 -> condFltReg GTT x y
      MO_S_Ge F64 -> condFltReg GE x y
      MO_S_Lt F64 -> condFltReg LTT x y
      MO_S_Le F64 -> condFltReg LE x y
1390

1391
1392
      MO_Eq rep -> condIntReg EQQ x y
      MO_Ne rep -> condIntReg NE x y
1393

1394
1395
1396
1397
1398
1399
1400
1401
1402
      MO_S_Gt rep -> condIntReg GTT x y
      MO_S_Ge rep -> condIntReg GE x y
      MO_S_Lt rep -> condIntReg LTT x y
      MO_S_Le rep -> condIntReg LE x y
	      
      MO_U_Gt I32  -> condIntReg GTT x y
      MO_U_Ge I32  -> condIntReg GE x y
      MO_U_Lt I32  -> condIntReg LTT x y
      MO_U_Le I32  -> condIntReg LE x y
1403

1404
1405
1406
1407
      MO_U_Gt I16 -> condIntReg GU  x y
      MO_U_Ge I16 -> condIntReg GEU x y
      MO_U_Lt I16 -> condIntReg LU  x y
      MO_U_Le I16 -> condIntReg LEU x y
1408

1409
1410
      MO_Add I32 -> trivialCode I32 (ADD False False) x y
      MO_Sub I32 -> trivialCode I32 (SUB False False) x y
1411

1412
1413
      MO_S_MulMayOflo rep -> imulMayOflo rep x y
{-
1414
      -- ToDo: teach about V8+ SPARC div instructions
1415
1416
1417
1418
1419
1420
1421
1422
1423
      MO_S_Quot I32 -> idiv FSLIT(".div")  x y
      MO_S_Rem I32  -> idiv FSLIT(".rem")  x y
      MO_U_Quot I32 -> idiv FSLIT(".udiv")  x y
      MO_U_Rem I32  -> idiv FSLIT(".urem")  x y
-}
      MO_Add F32  -> trivialFCode F32 FADD  x y
      MO_Sub F32   -> trivialFCode F32  FSUB x y
      MO_Mul F32   -> trivialFCode F32  FMUL  x y
      MO_S_Quot F32   -> trivialFCode F32  FDIV x y
1424

1425
1426
1427
1428
      MO_Add F64   -> trivialFCode F64 FADD  x y
      MO_Sub F64   -> trivialFCode F64  FSUB x y
      MO_Mul F64   -> trivialFCode F64  FMUL x y
      MO_S_Quot F64   -> trivialFCode F64  FDIV x y
1429

1430
1431
1432
      MO_And rep   -> trivialCode rep (AND False) x y
      MO_Or rep    -> trivialCode rep (OR  False) x y
      MO_Xor rep   -> trivialCode rep (XOR False) x y
1433

1434
      MO_Mul rep -> trivialCode rep (SMUL False) x y
1435

1436
1437
1438
      MO_Shl rep   -> trivialCode rep SLL  x y
      MO_U_Shr rep   -> trivialCode rep SRL x y
      MO_S_Shr rep   -> trivialCode rep SRA x y
1439

1440
{-
1441
1442
1443
1444
1445
      MO_F32_Pwr  -> getRegister (StCall (Left FSLIT("pow")) CCallConv F64 
                                         [promote x, promote y])
		       where promote x = CmmMachOp MO_F32_to_Dbl [x]
      MO_F64_Pwr -> getRegister (StCall (Left FSLIT("pow")) CCallConv F64 
                                        [x, y])
1446
-}
1447
1448
      other -> pprPanic "getRegister(sparc) - binary CmmMachOp (1)" (pprMachOp mop)
  where
1449
    --idiv fn x y = getRegister (StCall (Left fn) CCallConv I32 [x, y])
1450
1451

    --------------------
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
    imulMayOflo :: MachRep -> CmmExpr -> CmmExpr -> NatM Register
    imulMayOflo rep a b = do
         (a_reg, a_code) <- getSomeReg a
	 (b_reg, b_code) <- getSomeReg b
	 res_lo <- getNewRegNat I32
	 res_hi <- getNewRegNat I32
	 let
	    shift_amt  = case rep of
			  I32 -> 31
			  I64 -> 63
			  _ -> panic "shift_amt"
	    code dst = a_code `appOL` b_code `appOL`
                       toOL [
                           SMUL False a_reg (RIReg b_reg) res_lo,
1466
                           RDY res_hi,
1467
                           SRA res_lo (RIImm (ImmInt shift_amt)) res_lo,
1468
1469
                           SUB False False res_lo (RIReg res_hi) dst
                        ]
1470
         return (Any I32 code)
1471

1472
getRegister (CmmLoad mem pk) = do
1473
1474
    Amode src code <- getAmode mem
    let
1475
    	code__2 dst = code `snocOL` LD pk src dst
1476
1477
    return (Any pk code__2)

1478
getRegister (CmmLit (CmmInt i _))
1479
1480
1481
1482
1483
  | fits13Bits i
  = let
    	src = ImmInt (fromInteger i)
    	code dst = unitOL (OR False g0 (RIImm src) dst)
    in
1484
    	return (Any I32 code)
1485

1486
1487
1488
getRegister (CmmLit lit)
  = let rep = cmmLitRep lit
	imm = litToImm lit
1489
    	code dst = toOL [
1490
1491
1492
    	    SETHI (HI imm) dst,
    	    OR False dst (RIImm (LO imm)) dst]
    in return (Any I32 code)
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595

#endif /* sparc_TARGET_ARCH */

#if powerpc_TARGET_ARCH
getRegister (CmmLoad mem pk)
  | pk /= I64
  = do
        Amode addr addr_code <- getAmode mem
        let code dst = ASSERT((regClass dst == RcDouble) == isFloatingRep pk)
                       addr_code `snocOL` LD pk dst addr
        return (Any pk code)

-- catch simple cases of zero- or sign-extended load
getRegister (CmmMachOp (MO_U_Conv I8 I32) [CmmLoad mem _]) = do
    Amode addr addr_code <- getAmode mem
    return (Any I32 (\dst -> addr_code `snocOL` LD I8 dst addr))

-- Note: there is no Load Byte Arithmetic instruction, so no signed case here

getRegister (CmmMachOp (MO_U_Conv I16 I32) [CmmLoad mem _]) = do
    Amode addr addr_code <- getAmode mem
    return (Any I32 (\dst -> addr_code `snocOL` LD I16 dst addr))

getRegister (CmmMachOp (MO_S_Conv I16 I32) [CmmLoad mem _]) = do
    Amode addr addr_code <- getAmode mem
    return (Any I32 (\dst -> addr_code `snocOL` LA I16 dst addr))

getRegister (CmmMachOp mop [x]) -- unary MachOps
  = case mop of
      MO_Not rep   -> trivialUCode rep NOT x

      MO_S_Conv F64 F32 -> trivialUCode F32 FRSP x
      MO_S_Conv F32 F64 -> conversionNop F64 x

      MO_S_Conv from to
        | from == to         -> conversionNop to x
	| isFloatingRep from -> coerceFP2Int from to x
	| isFloatingRep to   -> coerceInt2FP from to x

        -- narrowing is a nop: we treat the high bits as undefined
      MO_S_Conv I32 to -> conversionNop to x
      MO_S_Conv I16 I8 -> conversionNop I8 x
      MO_S_Conv I8 to -> trivialUCode to (EXTS I8) x
      MO_S_Conv I16 to -> trivialUCode to (EXTS I16) x

      MO_U_Conv from to
        | from == to -> conversionNop to x
        -- narrowing is a nop: we treat the high bits as undefined
      MO_U_Conv I32 to -> conversionNop to x
      MO_U_Conv I16 I8 -> conversionNop I8 x
      MO_U_Conv I8 to -> trivialCode to False AND x (CmmLit (CmmInt 255 I32))
      MO_U_Conv I16 to -> trivialCode to False AND x (CmmLit (CmmInt 65535 I32)) 

      MO_S_Neg F32      -> trivialUCode F32 FNEG x
      MO_S_Neg F64      -> trivialUCode F64 FNEG x
      MO_S_Neg rep      -> trivialUCode rep NEG x
      
    where
        conversionNop new_rep expr
            = do e_code <- getRegister expr
                 return (swizzleRegisterRep e_code new_rep)

getRegister (CmmMachOp mop [x, y]) -- dyadic PrimOps
  = case mop of
      MO_Eq F32 -> condFltReg EQQ x y
      MO_Ne F32 -> condFltReg NE  x y

      MO_S_Gt F32 -> condFltReg GTT x y
      MO_S_Ge F32 -> condFltReg GE  x y
      MO_S_Lt F32 -> condFltReg LTT x y
      MO_S_Le F32 -> condFltReg LE  x y

      MO_Eq F64 -> condFltReg EQQ x y
      MO_Ne F64 -> condFltReg NE  x y

      MO_S_Gt F64 -> condFltReg GTT x y
      MO_S_Ge F64 -> condFltReg GE  x y
      MO_S_Lt F64 -> condFltReg LTT x y
      MO_S_Le F64 -> condFltReg LE  x y

      MO_Eq rep -> condIntReg EQQ  (extendUExpr rep x) (extendUExpr rep y)
      MO_Ne rep -> condIntReg NE   (extendUExpr rep x) (extendUExpr rep y)

      MO_S_Gt rep -> condIntReg GTT  (extendSExpr rep x) (extendSExpr rep y)
      MO_S_Ge rep -> condIntReg GE   (extendSExpr rep x) (extendSExpr rep y)
      MO_S_Lt rep -> condIntReg LTT  (extendSExpr rep x) (extendSExpr rep y)
      MO_S_Le rep -> condIntReg LE   (extendSExpr rep x) (extendSExpr rep y)

      MO_U_Gt rep -> condIntReg GU   (extendUExpr rep x) (extendUExpr rep y)
      MO_U_Ge rep -> condIntReg GEU  (extendUExpr rep x) (extendUExpr rep y)
      MO_U_Lt rep -> condIntReg LU   (extendUExpr rep x) (extendUExpr rep y)
      MO_U_Le rep -> condIntReg LEU  (extendUExpr rep x) (extendUExpr rep y)

      MO_Add F32   -> trivialCodeNoImm F32 (FADD F32) x y
      MO_Sub F32   -> trivialCodeNoImm F32 (FSUB F32) x y
      MO_Mul F32   -> trivialCodeNoImm F32 (FMUL F32) x y
      MO_S_Quot F32   -> trivialCodeNoImm F32 (FDIV F32) x y
      
      MO_Add F64   -> trivialCodeNoImm F64 (FADD F64) x y
      MO_Sub F64   -> trivialCodeNoImm F64 (FSUB F64) x y
      MO_Mul F64   -> trivialCodeNoImm F64 (FMUL F64) x y
      MO_S_Quot F64   -> trivialCodeNoImm F64 (FDIV F64) x y

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         -- optimize addition with 32-bit immediate
         -- (needed for PIC)
      MO_Add I32 ->
        case y of
          CmmLit (CmmInt imm immrep) | Just _ <- makeImmediate I32 True (-imm)
            -> trivialCode I32 True ADD x (CmmLit $ CmmInt imm immrep)
          CmmLit lit
            -> do
                (src, srcCode) <- getSomeReg x
                let imm = litToImm lit
                    code dst = srcCode `appOL` toOL [
                                    ADDIS dst src (HA imm),
                                    ADD dst dst (RIImm (LO imm))
                                ]
                return (Any I32 code)
          _ -> trivialCode I32 True ADD x y

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      MO_Add rep -> trivialCode rep True ADD x y
      MO_Sub rep ->
        case y of    -- subfi ('substract from' with immediate) doesn't exist
          CmmLit (CmmInt imm immrep) | Just _ <- makeImmediate rep True (-imm)
            -> trivialCode rep True ADD x (CmmLit $ CmmInt (-imm) immrep)
          _ -> trivialCodeNoImm rep SUBF y x

      MO_Mul rep -> trivialCode rep True MULLW x y

      MO_S_MulMayOflo I32 -> trivialCodeNoImm I32 MULLW_MayOflo x y
      
      MO_S_MulMayOflo rep -> panic "S_MulMayOflo (rep /= I32): not implemented"
      MO_U_MulMayOflo rep -> panic "U_MulMayOflo: not implemented"

      MO_S_Quot rep -> trivialCodeNoImm rep DIVW (extendSExpr rep x) (extendSExpr rep y)
      MO_U_Quot rep -> trivialCodeNoImm rep DIVWU (extendUExpr rep x) (extendUExpr rep y)
      
      MO_S_Rem rep -> remainderCode rep DIVW (extendSExpr rep x) (extendSExpr rep y)
      MO_U_Rem rep -> remainderCode rep DIVWU (extendUExpr rep x) (extendUExpr rep y)
      
      MO_And rep   -> trivialCode rep False AND x y
      MO_Or rep    -> trivialCode rep False OR x y
      MO_Xor rep   -> trivialCode rep False XOR x y

      MO_Shl rep   -> trivialCode rep False SLW x y
      MO_S_Shr rep -> trivialCode rep False SRAW (extendSExpr rep x) y
      MO_U_Shr rep -> trivialCode rep False SRW (extendUExpr rep x) y

getRegister (CmmLit (CmmInt i rep))
  | Just imm <- makeImmediate rep True i
  = let
    	code dst = unitOL (LI dst imm)
    in
    	return (Any rep code)

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getRegister (CmmLit (CmmFloat f frep)) = do
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    lbl <- getNewLabelNat
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    dynRef <- cmmMakeDynamicReference addImportNat False lbl
    Amode addr addr_code <- getAmode dynRef
    let code dst = 
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	    LDATA ReadOnlyData  [CmmDataLabel lbl,
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				 CmmStaticLit (CmmFloat f frep)]
            `consOL` (addr_code `snocOL` LD frep dst addr)
    return (Any frep code)
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getRegister (CmmLit lit)
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  = let rep = cmmLitRep lit
        imm = litToImm lit
        code dst = toOL [
              LIS dst (HI imm),
              OR dst dst (RIImm (LO imm))
          ]
    in return (Any rep code)

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getRegister other = pprPanic "getRegister(ppc)" (pprExpr other)
    
    -- extend?Rep: wrap integer expression of type rep
    -- in a conversion to I32
extendSExpr I32 x = x
extendSExpr rep x = CmmMachOp (MO_S_Conv rep I32) [x]
extendUExpr I32 x = x
extendUExpr rep x = CmmMachOp (MO_U_Conv rep I32) [x]

#endif /* powerpc_TARGET_ARCH */


-- -----------------------------------------------------------------------------
--  The 'Amode' type: Memory addressing modes passed up the tree.

data Amode = Amode AddrMode InstrBlock

{-
Now, given a tree (the argument to an CmmLoad) that references memory,
produce a suitable addressing mode.

A Rule of the Game (tm) for Amodes: use of the addr bit must
immediately follow use of the code part, since the code part puts
values in registers which the addr then refers to.  So you can't put
anything in between, lest it overwrite some of those registers.  If
you need to do some other computation between the code part and use of
the addr bit, first store the effective address from the amode in a
temporary, then do the other computation, and then use the temporary:

    code
    LEA amode, tmp
    ... other computation ...
    ... (tmp) ...
-}

getAmode :: CmmExpr -> NatM Amode
getAmode tree@(CmmRegOff _ _) = getAmode (mangleIndexTree tree)

-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

#if alpha_TARGET_ARCH

getAmode (StPrim IntSubOp [x, StInt i])
  = getNewRegNat PtrRep		`thenNat` \ tmp ->
    getRegister x		`thenNat` \ register ->
    let
    	code = registerCode register tmp
    	reg  = registerName register tmp
    	off  = ImmInt (-(fromInteger i))
    in
    return (Amode (AddrRegImm reg off) code)

getAmode (StPrim IntAddOp [x, StInt i])
  = getNewRegNat PtrRep		`thenNat` \ tmp ->
    getRegister x		`thenNat` \ register ->
    let
    	code = registerCode register tmp
    	reg  = registerName register tmp
    	off  = ImmInt (fromInteger i)
    in
    return (Amode (AddrRegImm reg off) code)

getAmode leaf
  | isJust imm
  = return (Amode (AddrImm imm__2) id)
  where
    imm = maybeImm leaf
    imm__2 = case imm of Just x -> x

getAmode other
  = getNewRegNat PtrRep		`thenNat` \ tmp ->
    getRegister other		`thenNat` \ register ->
    let
    	code = registerCode register tmp
    	reg  = registerName register tmp
    in
    return (Amode (AddrReg reg) code)

#endif /* alpha_TARGET_ARCH */

-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

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#if i386_TARGET_ARCH || x86_64_TARGET_ARCH
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-- This is all just ridiculous, since it carefully undoes 
-- what mangleIndexTree has just done.
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getAmode (CmmMachOp (MO_Sub rep) [x, CmmLit lit@(CmmInt i _)])
  | not (is64BitLit lit)
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  -- ASSERT(rep == I32)???
  = do (x_reg, x_code) <- getSomeReg x
       let off = ImmInt (-(fromInteger i))
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       return (Amode (AddrBaseIndex (EABaseReg x_reg) EAIndexNone off) x_code)
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getAmode (CmmMachOp (MO_Add rep) [x, CmmLit lit@(CmmInt i _)])
  | not (is64BitLit lit)
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  -- ASSERT(rep == I32)???
  = do (x_reg, x_code) <- getSomeReg x
       let off = ImmInt (fromInteger i)
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       return (Amode (AddrBaseIndex (EABaseReg x_reg)