Commit 7d817d44 authored by Ian Lynagh's avatar Ian Lynagh
Browse files

Fix truncate on amd64 NCG; fixes arith005.

cvts[sd]2siq? ->
cvtts[sd]2siq?
parent 44860c92
......@@ -4563,6 +4563,8 @@ remainderCode rep div x y = do
-- -----------------------------------------------------------------------------
-- Coercing to/from integer/floating-point...
-- When going to integer, we truncate (round towards 0).
-- @coerce(Int2FP|FP2Int)@ are more complicated integer/float
-- conversions. We have to store temporaries in memory to move
-- between the integer and the floating point register sets.
......@@ -4648,7 +4650,7 @@ coerceFP2Int from to x = do
coerceFP2Int from to x = do
(x_op, x_code) <- getOperand x -- ToDo: could be a safe operand
let
opc = case from of F32 -> CVTSS2SI; F64 -> CVTSD2SI
opc = case from of F32 -> CVTTSS2SIQ; F64 -> CVTTSD2SIQ
code dst = x_code `snocOL` opc x_op dst
-- in
return (Any to code) -- works even if the destination rep is <I32
......
......@@ -488,8 +488,8 @@ bit or 64 bit precision.
| CVTSS2SD Reg Reg -- F32 to F64
| CVTSD2SS Reg Reg -- F64 to F32
| CVTSS2SI Operand Reg -- F32 to I32/I64 (with rounding)
| CVTSD2SI Operand Reg -- F64 to I32/I64 (with rounding)
| CVTTSS2SIQ Operand Reg -- F32 to I32/I64 (with truncation)
| CVTTSD2SIQ Operand Reg -- F64 to I32/I64 (with truncation)
| CVTSI2SS Operand Reg -- I32/I64 to F32
| CVTSI2SD Operand Reg -- I32/I64 to F64
......
......@@ -1310,8 +1310,8 @@ pprInstr (FDIV size op1 op2) = pprSizeOpOp SLIT("div") size op1 op2
pprInstr (CVTSS2SD from to) = pprRegReg SLIT("cvtss2sd") from to
pprInstr (CVTSD2SS from to) = pprRegReg SLIT("cvtsd2ss") from to
pprInstr (CVTSS2SI from to) = pprOpReg SLIT("cvtss2siq") from to
pprInstr (CVTSD2SI from to) = pprOpReg SLIT("cvtsd2siq") from to
pprInstr (CVTTSS2SIQ from to) = pprOpReg SLIT("cvttss2siq") from to
pprInstr (CVTTSD2SIQ from to) = pprOpReg SLIT("cvttsd2siq") from to
pprInstr (CVTSI2SS from to) = pprOpReg SLIT("cvtsi2ssq") from to
pprInstr (CVTSI2SD from to) = pprOpReg SLIT("cvtsi2sdq") from to
#endif
......
......@@ -214,8 +214,8 @@ regUsage instr = case instr of
#if x86_64_TARGET_ARCH
CVTSS2SD src dst -> mkRU [src] [dst]
CVTSD2SS src dst -> mkRU [src] [dst]
CVTSS2SI src dst -> mkRU (use_R src) [dst]
CVTSD2SI src dst -> mkRU (use_R src) [dst]
CVTTSS2SIQ src dst -> mkRU (use_R src) [dst]
CVTTSD2SIQ src dst -> mkRU (use_R src) [dst]
CVTSI2SS src dst -> mkRU (use_R src) [dst]
CVTSI2SD src dst -> mkRU (use_R src) [dst]
FDIV sz src dst -> usageRM src dst
......@@ -588,8 +588,8 @@ patchRegs instr env = case instr of
#if x86_64_TARGET_ARCH
CVTSS2SD src dst -> CVTSS2SD (env src) (env dst)
CVTSD2SS src dst -> CVTSD2SS (env src) (env dst)
CVTSS2SI src dst -> CVTSS2SI (patchOp src) (env dst)
CVTSD2SI src dst -> CVTSD2SI (patchOp src) (env dst)
CVTTSS2SIQ src dst -> CVTTSS2SIQ (patchOp src) (env dst)
CVTTSD2SIQ src dst -> CVTTSD2SIQ (patchOp src) (env dst)
CVTSI2SS src dst -> CVTSI2SS (patchOp src) (env dst)
CVTSI2SD src dst -> CVTSI2SD (patchOp src) (env dst)
FDIV sz src dst -> FDIV sz (patchOp src) (patchOp dst)
......
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