Commit 846f2649 authored by rl@cse.unsw.edu.au's avatar rl@cse.unsw.edu.au
Browse files

Add atomic SMP primitives for the Sparc

parent 1777f480
...@@ -48,6 +48,13 @@ xchg(StgPtr p, StgWord w) ...@@ -48,6 +48,13 @@ xchg(StgPtr p, StgWord w)
:"=r" (result) :"=r" (result)
:"r" (w), "r" (p) :"r" (w), "r" (p)
); );
#elif sparc_HOST_ARCH
result = w;
__asm__ __volatile__ (
"swap %1,%0"
: "+r" (result), "+m" (*p)
: /* no input-only operands */
);
#elif !defined(WITHSMP) #elif !defined(WITHSMP)
result = *p; result = *p;
*p = w; *p = w;
...@@ -84,6 +91,14 @@ cas(StgVolatilePtr p, StgWord o, StgWord n) ...@@ -84,6 +91,14 @@ cas(StgVolatilePtr p, StgWord o, StgWord n)
:"cc", "memory" :"cc", "memory"
); );
return result; return result;
#elif sparc_HOST_ARCH
__asm__ __volatile__ (
"cas [%1], %2, %0"
: "+r" (n)
: "r" (p), "r" (o)
: "memory"
);
return n;
#elif !defined(WITHSMP) #elif !defined(WITHSMP)
StgWord result; StgWord result;
result = *p; result = *p;
...@@ -112,6 +127,9 @@ write_barrier(void) { ...@@ -112,6 +127,9 @@ write_barrier(void) {
__asm__ __volatile__ ("" : : : "memory"); __asm__ __volatile__ ("" : : : "memory");
#elif powerpc_HOST_ARCH #elif powerpc_HOST_ARCH
__asm__ __volatile__ ("lwsync" : : : "memory"); __asm__ __volatile__ ("lwsync" : : : "memory");
#elif sparc_HOST_ARCH
/* Sparc in TSO mode does not require write/write barriers. */
__asm__ __volatile__ ("" : : : "memory");
#elif !defined(WITHSMP) #elif !defined(WITHSMP)
return; return;
#else #else
......
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