Fix code generation for SSE vector operations
The new implementation generates correct code even if the registers overlap. Closes #25859
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- compiler/GHC/CmmToAsm/X86/CodeGen.hs 16 additions, 6 deletionscompiler/GHC/CmmToAsm/X86/CodeGen.hs
- testsuite/tests/simd/should_run/all.T 10 additions, 0 deletionstestsuite/tests/simd/should_run/all.T
- testsuite/tests/simd/should_run/doublex2_arith.hs 95 additions, 0 deletionstestsuite/tests/simd/should_run/doublex2_arith.hs
- testsuite/tests/simd/should_run/doublex2_arith.stdout 21 additions, 0 deletionstestsuite/tests/simd/should_run/doublex2_arith.stdout
- testsuite/tests/simd/should_run/doublex2_arith_baseline.hs 95 additions, 0 deletionstestsuite/tests/simd/should_run/doublex2_arith_baseline.hs
- testsuite/tests/simd/should_run/doublex2_arith_baseline.stdout 21 additions, 0 deletions...uite/tests/simd/should_run/doublex2_arith_baseline.stdout
- testsuite/tests/simd/should_run/doublex2_fma.hs 133 additions, 0 deletionstestsuite/tests/simd/should_run/doublex2_fma.hs
- testsuite/tests/simd/should_run/doublex2_fma.stdout 48 additions, 0 deletionstestsuite/tests/simd/should_run/doublex2_fma.stdout
- testsuite/tests/simd/should_run/floatx4_arith.hs 95 additions, 0 deletionstestsuite/tests/simd/should_run/floatx4_arith.hs
- testsuite/tests/simd/should_run/floatx4_arith.stdout 21 additions, 0 deletionstestsuite/tests/simd/should_run/floatx4_arith.stdout
- testsuite/tests/simd/should_run/floatx4_arith_baseline.hs 95 additions, 0 deletionstestsuite/tests/simd/should_run/floatx4_arith_baseline.hs
- testsuite/tests/simd/should_run/floatx4_arith_baseline.stdout 21 additions, 0 deletions...suite/tests/simd/should_run/floatx4_arith_baseline.stdout
- testsuite/tests/simd/should_run/floatx4_fma.hs 133 additions, 0 deletionstestsuite/tests/simd/should_run/floatx4_fma.hs
- testsuite/tests/simd/should_run/floatx4_fma.stdout 48 additions, 0 deletionstestsuite/tests/simd/should_run/floatx4_fma.stdout
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