Finish pass 1 over the build system docs.

Fix some of the gross inaccuracies in this documentation.

Removed version number and reelucidated some text swallowed by index entries.

Changed default text size to "normal".

spillReg, loadReg (x86): spill above %esp, not below it.  Duh.  If you
spill below %esp, ccalls, which use stack below %esp, can trash the
spill area.

Updated version to 4.06

Sven's first autoheader commandment: Don't change config.h.in manually...!
(Why is mk/config.h.in in the repository? configure is not, either.)

Teach magicIdRegMaybe about R9 and R10.

Print a useful panic msg if getRegister(x86) can't reduce a tree.

pprInstr: implement GABS, GNEG, GSQRT.

Handle float args correctly for x86 ccalls.

Disable a dubious looking clause for trivialCode (x86), which was
generating bad code for some subtracts.

Implement the HP_CHK_GEN macro.  As a result, teach mkNativeHdr et al
about R9 and R10.

wibble

amodeToStix, GET_TAG: implement correctly for little-endian-32 and
supply implementation for big-endian-32.  Definitely won't work on
64-bit platforms.

genCodeInfoTable: put tag value into srt_len field for constr info tables.

"installing" is now called "building"

x86: free up all FP regs before doing a ccall.  This appears to be a
part of the x86 calling convention(s).

Added a bunch of #defines for {SIZEOF,ALIGNMENT}_{INT,WORD}{8,16,32,64}.
All this is a real hack: The include files need a more thorough restructuring.

Added note about necessary synching with MachDeps.h and fixed a small typo

Added more SIZEOF/ALIGNMENT tests

fix typo

Renamed from installing.sgml

Renamed to building.sgml

Corrected some URLs

Added an ID to the exceptions update section to use as a hyperlink destination

Announce 4.06

urk, Solaris sh doesn't understand [^0-9] in patterns, it seems.

Add missing final paragraph of explaination about x86 FP trickery.

Minor improvements to x86 FP fake-to-real insn translation.

genCCall for x86, as supplied, used PUSH et al to move args onto the C
stack ready for the call.  Reasonable as this seems, it causes a
problem with spill code, since the spiller spills relative to %esp and
assumes that %esp doesn't move.  If the args of a ccall involved any
spilled values, the resulting code would be wrong.

The One True Way is to do it like a RISC: move args to the stack
without adjusting %esp for each argument, then adjust it all at once
immediately prior to the call insn and un-adjust it immediately
afterwards.  genCCall now does this.  In general, push/pop and other
C-stack effecting operations should not be generated for the same
reason.

Add -optCrts-M80m for older compilers.  Sigh.

Added intToWord to PrelAddr.
Use it instead of int2Word#-hacks.

Start a NOTES file, recording known but un-fixed nativeGen bugs.

Fix syntax errors in #ifdef'd Alpha/Sparc bits.

Insert large commit message re x86 FP rehash as a comment.

ARR_HDR_SIZE --> ARR_WORDS_HDR_SIZE, and derived quantities in
Constants.h, Constants.lhs et al are similarly renamed.

new constant ARR_PTRS_HDR_SIZE, with corresponding derivatives.

Changed default paper size for SGML output to A4 (%paper-type%).

Major reworking of the x86 floating point code generation.

Intel, in their infinite wisdom, selected a stack model for floating
point registers on x86.  That might have made sense back in 1979 --
nowadays we can see it for the nonsense it really is.  A stack model
fits poorly with the existing nativeGen infrastructure, which assumes
flat integer and FP register sets.  Prior to this commit, nativeGen
could not generate correct x86 FP code -- to do so would have meant
somehow working the register-stack paradigm into the register
allocator and spiller, which sounds very difficult.

We have decided to cheat, and go for a simple fix which requires no
infrastructure modifications, at the expense of generating ropey but
correct FP code.  All notions of the x86 FP stack and its insns have
been removed.  Instead, we pretend (to the instruction selector and
register allocator) that x86 has six floating point registers, %fake0
.. %fake5, which can be used in the usual flat manner.  We further
claim that x86 has floating point instructions very similar to SPARC
and Alpha, that is, a simple 3-operand register-register arrangement.
Code generation and register allocation proceed on this basis.

When we come to print out the final assembly, our convenient fiction
is converted to dismal reality.  Each fake instruction is
independently converted to a series of real x86 instructions.
%fake0 .. %fake5 are mapped to %st(0) .. %st(5).  To do reg-reg
arithmetic operations, the two operands are pushed onto the top of the
FP stack, the operation done, and the result copied back into the
relevant register.  There are only six %fake registers because 2 are
needed for the translation, and x86 has 8 in total.

The translation is inefficient but is simple and it works.  A cleverer
translation would handle a sequence of insns, simulating the FP stack
contents, would not impose a fixed mapping from %fake to %st regs, and
hopefully could avoid most of the redundant reg-reg moves of the
current translation.

Added table example.