Make sure we don't emit slow `lea` instructions.

Prompted by this: https://reviews.llvm.org/D32277

It seems certain lea instruction variants are punished in newer intel CPUS.

According to Intel's Optimization Reference Manual for SNB+:
" For LEA instructions with three source operands and some specific situations, instruction latency has increased to 3 cycles, and must
  dispatch via port 1:
- LEA that has all three source operands: base, index, and offset
- LEA that uses base and index registers where the base is EBP, RBP,or R13
- LEA that uses RIP relative addressing mode
- LEA that uses 16-bit addressing mode "

The tasks to perform are then:

Confirm this is still the case for current-gen cpus (the llvm patch/issue is from 2017). Appropriate sources for this are the intel manual and agner fogs instructions performance tables.
If it still applies introduce checks for these conditions in the NCG to avoid emitting such instructions.
(Optional) Check if this also applies for AMD and introduce a flag to control this behaviour.

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