AVX/SSE4 SIMD support for the native code generator

This is a cleaned-up version of Abhiroop Sarkar's GSoC project from last year which added support for the basic vector arithmetic, extract, and broadcasting operations provided by AVX to the native code generator.

changed milestone to %8.10.1

added NCG backend SIMD labels

added 4 commits

• ac03f0f4 - Refactor treatment of YMM and ZMM registers
• 2008527d - A lot of refactoring
• eec35594 - Rename SIMD tests
• 062b39a8 - Drop stale comment

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added 1 commit

• 82b2864a - Fix whitespace

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added 1 commit

• 80821979 - Add support for SIMD operations in the NCG

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added 5 commits

• 6392b6bf - Improve debug output on register spill failure
• 4563495b - Use Outputable of VirtualReg
• cdd61acf - Missing patterns
• 73ba3247 - Yes
• 19e47100 - Rip out RcVector

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added 15 commits

• 19e47100...bd660ede - 13 commits from branch master
• f1c01dfd - Add support for SIMD operations in the NCG
• e14d6648 - hi

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added 1 commit

• ff823a08 - Add support for SIMD operations in the NCG

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approved this merge request

assigned to @marge-bot

I will attempt to batch this MR (!1342 (closed))...

Merged in acd79558

closed