WIP: ARM NCG

ARM Backend

Advanced RISC Machine (ARMv8) native code generation backend for GHC.

Phase 1

• Successfully compile ADD using @bgamari's https://gitlab.haskell.org/bgamari/asm-test

Configuration

• Ensure GHC is configured to allow -fasm on ARM machines (update config.mk)
• Update Hadrian build system to support native ARM builds.

Instructions (Instr.hs)

• Add ARM/Instr.hs stub
• Add ARM.Instr sum type of ARM ISA with correct operands.
• Implement Instruction class on ARM.Instr
• Implement maxSpillSlots
• Implement makeFarBranches
• Handle additional stack allocation (i.e. allocMoreStack)

Conditionals (Cond.hs)

• Add ARM/Cond.hs
• Define ARM conditionals
• Add condNegate

Pretty printing (Ppr.hs)

• Add ARM/Ppr.hs
• Implement pretty-printing to SDoc for all ARM instructions

Register Layout (Regs.hs/RegInfo.hs)

• Add ARM/Regs.hs
• Generalize to support both 32-bit / 64-bit (ARMv7 & ARMv8) .. see X86/Regs.hs
• Implement getJumpDestBlockId, canShortcut, shortcutStatics, shortcutJump
• Implement allocatableRegs
• Define Register layout
  • Immediates
  • Registers
  • Addressing modes
  • Squeeze functions

CodeGen (CodeGen.hs)

• Add ARM/CodeGen.hs
• Implement cmmTopCodeGen :: RawCmmDecl -> NatM [NatCmmDecl RawCmmStatics Instr]
• Implement generateJumpTableForInstr

Register allocator

• Add compiler/GHC/CmmToAsm/Reg/Linear/ARM.hs
• Implement ARM Linear register allocator functions

Position independent code

• Account for -fPic