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Correct load_load_barrier for risc-v

Takenobu Tani requested to merge takenobu-hs/ghc:wip/load_barrier_riscv into master

This patch corrects the instruction for load_load_barrier(). Current load_load_barrier() incorrectly uses fence w,r. It means a store-load barrier.

See also linux-kernel's smp_rmb() implementation:

I've only checked this patch statically. I haven't validated this patch on a RISC-V machine.

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