Correct load_load_barrier for risc-v

This patch corrects the instruction for load_load_barrier(). Current load_load_barrier() incorrectly uses fence w,r. It means a store-load barrier.

See also linux-kernel's smp_rmb() implementation:

• https://github.com/torvalds/linux/blob/v5.14/arch/riscv/include/asm/barrier.h#L27

I've only checked this patch statically. I haven't validated this patch on a RISC-V machine.