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Various memory ordering fixes

Ben Gamari requested to merge wip/tsan/fixes into master

This is a follow-up to !6232 (closed), fixing the issues identified by TSAN:

  • Drop (nearly) all memory barriers from hand-written Cmm in favour of ordered loads and stored (or, in a few places, explicitly-ordered fences)
  • Elaborate on Note [Heap memory barriers], which now contains a much more convincing soundness story
  • Fix a few issues in ghc itself where IORefs are incorrectly used with an expectation of thread-safety
  • Encapsulate various bits of RTS mutable global state (n_capabilities, sched_state, recent_activity) and access them only through accessors which use the necessary atomic operations
  • Fix a data race in readTVarIO#
  • Fix a data race in makeStableName#
  • Move to a statically-allocated Capabilities array to avoid a rather tricky data race between the timer (which may be implemented by way of a signal) and setNumCapabilities (which previously reallocated the global capabilities array)

This is based on !6232 (closed).

Edited by Ben Gamari

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