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# Memory ordering
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This page describes the memory ordering design in GHC.
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Please update this page freely.
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## Background
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There are various architectures about memory ordering (see [here](https://en.wikipedia.org/wiki/Memory_ordering)).
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GHC needs to correspond to each sort.
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* Strong memory ordering (TSO):
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* X86, SPARC in TSO mode
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* Weak memory ordering:
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* ARM, PowerPC
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On weakly ordering machines, store-store and load-load instructions may be also reorderd.
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So we need appropriate memory barriers.
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## Heap memory barriers
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Here is the design note about heap memory barriers in GHC:
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* `Note [Heap memory barriers]` in [includes/stg/SMP.h](https://gitlab.haskell.org/ghc/ghc/blob/master/includes/stg/SMP.h)
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Related marge request and mails are here:
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* https://gitlab.haskell.org/ghc/ghc/merge_requests/1128 (originaly https://gitlab.haskell.org/ghc/ghc/merge_requests/734)
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* [Cmm Memory Model (Understanding #15449)](https://mail.haskell.org/pipermail/ghc-devs/2018-November/016581.html) at ghc-devs ML.
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## Related documents and articles
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Here are some useful resources:
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- [The JSR-133 Cookbook for Compiler Writers](http://g.oswego.edu/dl/jmm/cookbook.html)
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- [LINUX KERNEL MEMORY BARRIERS](https://github.com/torvalds/linux/blob/master/Documentation/memory-barriers.txt)
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- [Memory ordering](https://en.wikipedia.org/wiki/Memory_ordering)
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- [LLVM Language Reference Manual, ‘cmpxchg’ Instruction](https://llvm.org/docs/LangRef.html#cmpxchg-instruction) |