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**This page is obsolete**. Please see the [top-level SIMD project page](simd) for further details.
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# Using SIMD Instructions via the LLVM Backend
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... | ... | @@ -6,12 +8,6 @@ The LLVM compiler tools targeted by GHC's [LLVM backend](commentary/compiler/bac |
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The SIMD vector extension to GHC proposed here maps to LLVM's vector type in a straight forward manner, which in turn enables us to target a wide range of hardware capabilities. However, GHC's native code generator will simply map SIMD vector operations to ordinary scalar code (in order to avoid having to deal with the complexities of SSE, AVX, NEON, etc).
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Related pages
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- [Implementation plan](simd-plan)
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- There is also also the outdated [VectorComputing](vector-computing).
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## Variations in the most widely used SIMD extensions
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... | ... | @@ -143,8 +139,3 @@ In DPH, we will use the new SIMD instructions by suitably modifying the definiti |
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We could define them more verbosely using a plain `VECTORISE` pragma, but might instead like to extend `VECTORISE SCALAR` or introduce a variant.
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**NB:** The use of SIMD instructions interferes with vectorisation avoidance for scalar subcomputations. Code that avoids vectorisation also avoids the use of SIMD instructions. We would like to use SIMD instructions, but still avoid full-scale vectorisation. This should be possible, but it is not immediately clear how to realise it (elegantly). |
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## Implementation Details and Plan
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For implementation details and a plan, refer to the [SIMD Implementation Details and Plan](simd-plan) Page |