add missing cases for ArchARM

compiler/nativeGen/AsmCodeGen.lhs

@@ -197,6 +197,8 @@ nativeCodeGen dflags h us cmms
                          ,ncgExpandTop              = map SPARC.CodeGen.Expand.expandTop
                          ,ncgMakeFarBranches        = id
                      }
+                 ArchARM ->
+                     panic "nativeCodeGen: No NCG for ARM"
                  ArchPPC_64 ->
                      panic "nativeCodeGen: No NCG for PPC 64"
                  ArchUnknown ->

compiler/nativeGen/RegAlloc/Graph/TrivColorable.hs

@@ -115,6 +115,7 @@ trivColorable virtualRegSqueeze realRegSqueeze RcInteger conflicts exclusions
                             ArchPPC     -> 16
                             ArchSPARC   -> 14
                             ArchPPC_64  -> panic "trivColorable ArchPPC_64"
+                            ArchARM     -> panic "trivColorable ArchARM"
                             ArchUnknown -> panic "trivColorable ArchUnknown")
         , count2        <- accSqueeze (_ILIT(0)) cALLOCATABLE_REGS_INTEGER
                                 (virtualRegSqueeze RcInteger)
@@ -134,6 +135,7 @@ trivColorable virtualRegSqueeze realRegSqueeze RcFloat conflicts exclusions
                             ArchPPC     -> 0
                             ArchSPARC   -> 22
                             ArchPPC_64  -> panic "trivColorable ArchPPC_64"
+                            ArchARM     -> panic "trivColorable ArchARM"
                             ArchUnknown -> panic "trivColorable ArchUnknown")
         , count2        <- accSqueeze (_ILIT(0)) cALLOCATABLE_REGS_FLOAT
                                 (virtualRegSqueeze RcFloat)
@@ -153,6 +155,7 @@ trivColorable virtualRegSqueeze realRegSqueeze RcDouble conflicts exclusions
                             ArchPPC     -> 26
                             ArchSPARC   -> 11
                             ArchPPC_64  -> panic "trivColorable ArchPPC_64"
+                            ArchARM     -> panic "trivColorable ArchARM"
                             ArchUnknown -> panic "trivColorable ArchUnknown")
         , count2        <- accSqueeze (_ILIT(0)) cALLOCATABLE_REGS_DOUBLE
                                 (virtualRegSqueeze RcDouble)
@@ -172,6 +175,7 @@ trivColorable virtualRegSqueeze realRegSqueeze RcDoubleSSE conflicts exclusions
                             ArchPPC     -> 0
                             ArchSPARC   -> 0
                             ArchPPC_64  -> panic "trivColorable ArchPPC_64"
+                            ArchARM     -> panic "trivColorable ArchARM"
                             ArchUnknown -> panic "trivColorable ArchUnknown")
         , count2        <- accSqueeze (_ILIT(0)) cALLOCATABLE_REGS_SSE
                                 (virtualRegSqueeze RcDoubleSSE)

compiler/nativeGen/RegAlloc/Linear/FreeRegs.hs

@@ -68,6 +68,7 @@ maxSpillSlots = case platformArch defaultTargetPlatform of
                 ArchX86_64  -> X86.Instr.maxSpillSlots
                 ArchPPC     -> PPC.Instr.maxSpillSlots
                 ArchSPARC   -> SPARC.Instr.maxSpillSlots
+                ArchARM     -> panic "maxSpillSlots ArchARM"
                 ArchPPC_64  -> panic "maxSpillSlots ArchPPC_64"
                 ArchUnknown -> panic "maxSpillSlots ArchUnknown"
 

compiler/nativeGen/RegAlloc/Linear/Main.hs

@@ -183,6 +183,7 @@ linearRegAlloc dflags first_id block_live sccs
    ArchX86_64  -> linearRegAlloc' (frInitFreeRegs :: X86.FreeRegs)   first_id block_live sccs
    ArchSPARC   -> linearRegAlloc' (frInitFreeRegs :: SPARC.FreeRegs) first_id block_live sccs
    ArchPPC     -> linearRegAlloc' (frInitFreeRegs :: PPC.FreeRegs)   first_id block_live sccs
+   ArchARM     -> panic "linearRegAlloc ArchARM"
    ArchPPC_64  -> panic "linearRegAlloc ArchPPC_64"
    ArchUnknown -> panic "linearRegAlloc ArchUnknown"
 

compiler/nativeGen/TargetReg.hs

@@ -52,6 +52,7 @@ targetVirtualRegSqueeze
       ArchPPC     -> PPC.virtualRegSqueeze
       ArchSPARC   -> SPARC.virtualRegSqueeze
       ArchPPC_64  -> panic "targetVirtualRegSqueeze ArchPPC_64"
+      ArchARM     -> panic "targetVirtualRegSqueeze ArchARM"
       ArchUnknown -> panic "targetVirtualRegSqueeze ArchUnknown"
 
 targetRealRegSqueeze :: RegClass -> RealReg -> FastInt
@@ -62,6 +63,7 @@ targetRealRegSqueeze
       ArchPPC     -> PPC.realRegSqueeze
       ArchSPARC   -> SPARC.realRegSqueeze
       ArchPPC_64  -> panic "targetRealRegSqueeze ArchPPC_64"
+      ArchARM     -> panic "targetRealRegSqueeze ArchARM"
       ArchUnknown -> panic "targetRealRegSqueeze ArchUnknown"
 
 targetClassOfRealReg :: RealReg -> RegClass
@@ -72,6 +74,7 @@ targetClassOfRealReg
       ArchPPC     -> PPC.classOfRealReg
       ArchSPARC   -> SPARC.classOfRealReg
       ArchPPC_64  -> panic "targetClassOfRealReg ArchPPC_64"
+      ArchARM     -> panic "targetClassOfRealReg ArchARM"
       ArchUnknown -> panic "targetClassOfRealReg ArchUnknown"
 
 -- TODO: This should look at targetPlatform too
@@ -86,6 +89,7 @@ targetMkVirtualReg
       ArchPPC     -> PPC.mkVirtualReg
       ArchSPARC   -> SPARC.mkVirtualReg
       ArchPPC_64  -> panic "targetMkVirtualReg ArchPPC_64"
+      ArchARM     -> panic "targetMkVirtualReg ArchARM"
       ArchUnknown -> panic "targetMkVirtualReg ArchUnknown"
 
 targetRegDotColor :: RealReg -> SDoc
@@ -96,6 +100,7 @@ targetRegDotColor
       ArchPPC     -> PPC.regDotColor
       ArchSPARC   -> SPARC.regDotColor
       ArchPPC_64  -> panic "targetRegDotColor ArchPPC_64"
+      ArchARM     -> panic "targetRegDotColor ArchARM"
       ArchUnknown -> panic "targetRegDotColor ArchUnknown"
 
 

compiler/nativeGen/X86/RegInfo.hs

@@ -61,6 +61,7 @@ normalRegColors = case platformArch defaultTargetPlatform of
                   ArchPPC     -> panic "X86 normalRegColors ArchPPC"
                   ArchPPC_64  -> panic "X86 normalRegColors ArchPPC_64"
                   ArchSPARC   -> panic "X86 normalRegColors ArchSPARC"
+                  ArchARM     -> panic "X86 normalRegColors ArchARM"
                   ArchUnknown -> panic "X86 normalRegColors ArchUnknown"
 
 fpRegColors :: [(Reg,String)]