nativeGen/aarch64: Fix handling of subword values

Here we rework the handling of sub-word operations in the AArch64
backend, fixing a number of bugs and inconsistencies. In short,
we now impose the invariant that all subword values are represented in
registers in zero-extended form. Signed arithmetic operations are then
responsible for sign-extending as necessary.

Possible future work:

 * Use `CMP`s extended register form to avoid burning an instruction
   in sign-extending the second operand.

 * Track sign-extension state of registers to elide redundant sign
   extensions in blocks with frequent sub-word signed arithmetic.