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We were emitting the wrong instructions for fused multiply-add operations on LLVM: - the instruction name is "llvm.fma.f32" or "llvm.fma.f64", not "fmadd" - LLVM does not support other instructions such as "fmsub"; instead we implement these by flipping signs of some arguments - the instruction is an LLVM intrinsic, which requires handling it like a normal function call instead of a machine instruction Fixes #24223We were emitting the wrong instructions for fused multiply-add operations on LLVM: - the instruction name is "llvm.fma.f32" or "llvm.fma.f64", not "fmadd" - LLVM does not support other instructions such as "fmsub"; instead we implement these by flipping signs of some arguments - the instruction is an LLVM intrinsic, which requires handling it like a normal function call instead of a machine instruction Fixes #24223
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Ben.dump-ds-preopt 1.13 KiB
==================== Desugar (before optimization) ====================
2023-09-19 16:22:12.5377082 UTC
Result size of Desugar (before optimization)
= {terms: 14, types: 51, coercions: 21, joins: 0/1}
Rec {
-- RHS size: {terms: 13, types: 40, coercions: 21, joins: 0/1}
foo :: forall {s} a. a -> State# s -> (# Int#, State# s #)
[LclIdX]
foo
= \ (@s_al6) (@a_al7) ->
let {
irred_ale :: GHC.Prim.SmallRep# (TupleRep [IntRep, ZeroBitRep])
[LclId]
irred_ale
= (CO: <TupleRep [IntRep, ZeroBitRep]>_N)
`cast` (Sub (Sym (AxSmallRep# (<TupleRep [IntRep, ZeroBitRep]>_N)))
:: (TupleRep [IntRep, ZeroBitRep]
GHC.Prim.~# TupleRep [IntRep, ZeroBitRep])
~R# GHC.Prim.SmallRep# (TupleRep [IntRep, ZeroBitRep])) } in
\ (x_akF :: a_al7) (s0_akG :: State# s_al6) ->
keepAlive#
@(TupleRep [IntRep, ZeroBitRep])
@Lifted
@a_al7
@s_al6
@(# Int#, State# s_al6 #)
irred_ale
x_akF
s0_akG
(\ (s1_akH :: State# s_al6) -> (# 42#, s1_akH #))
end Rec }